2; File Name: cydevicerv_trm.inc
7; This file provides all of the address values
for the entire PSoC device.
9;-------------------------------------------------------------------------------
10; Copyright (c) 2007-2020 Cypress Semiconductor. All rights reserved.
11; You may use
this file only in accordance with the license, terms, conditions,
12; disclaimers, and limitations in the end user license agreement accompanying
13; the software
package with which this file was provided.
14;-------------------------------------------------------------------------------
#define CYCLK_SRC_SEL_DSI_G
#define CYDEV_IO_DR_PRT1_BASE
#define CYDEV_MFGCFG_ANAIF_DAC3_SIZE
#define CYDEV_MFGCFG_XMHZ_SIZE
#define CYDEV_PICU_STAT_PICU5_BASE
#define CYDEV_CAN0_RX1_SIZE
#define CYDEV_UWRK_UWRK16_BASE
#define CYDEV_UCFG_B0_P4_U0_BASE
#define CYDEV_UCFG_B0_P2_ROUTE_BASE
#define CYDEV_PICU_STAT_PICU12_SIZE
#define CYDEV_IO_PC_PRT5_SIZE
#define CYDEV_FASTCLK_XMHZ_BASE
#define CYDEV_PHUB_TDMEM6_SIZE
#define CYDEV_CAN0_RX6_BASE
#define CYDEV_CAN0_RX5_SIZE
#define CYDEV_PHUB_TDMEM62_BASE
#define CYDEV_PHUB_TDMEM99_BASE
#define CYDEV_PHUB_TDMEM8_SIZE
#define CYDEV_PHUB_TDMEM86_BASE
#define CYDEV_UCFG_B0_P0_ROUTE_SIZE
#define CYDEV_UCFG_DSI12_BASE
#define CYDEV_CLKDIST_ACFG2_BASE
#define CYDEV_UWRK_UWRK8_B0_BASE
#define CYDEV_UCFG_B0_P1_SIZE
#define CYDEV_CAN0_TX2_SIZE
#define CYDEV_PICU_STAT_PICU3_BASE
#define CYDEV_ANAIF_WRK_SC_SIZE
#define CYDEV_IO_PRT_BASE
#define CYDEV_PHUB_TDMEM82_SIZE
#define CYDEV_MFGCFG_ANAIF_CMP0_BASE
#define CYDEV_PHUB_TDMEM30_BASE
#define CYDEV_PHUB_TDMEM83_BASE
#define CYDEV_ANAIF_WRK_SAR0_SIZE
#define CYDEV_PICU_SNAP_PICU2_SIZE
#define CYDEV_PHUB_TDMEM12_BASE
#define CYDEV_PHUB_TDMEM31_BASE
#define CYDEV_ANAIF_CFG_DAC3_SIZE
#define CYDEV_IO_DR_PRT1_SIZE
#define CYDEV_PICU_STAT_PICU15_SIZE
#define CYDEV_PHUB_TDMEM19_SIZE
#define CYDEV_PHUB_TDMEM8_BASE
#define CYDEV_PHUB_CFGMEM17_BASE
#define CYDEV_PHUB_TDMEM126_SIZE
#define CYDEV_PHUB_CH23_SIZE
#define CYDEV_CAN0_RX12_SIZE
#define CYDEV_PHUB_TDMEM2_SIZE
#define CYDEV_PHUB_TDMEM40_BASE
#define CYDEV_CAN0_RX2_BASE
#define CYDEV_CLKDIST_ACFG3_SIZE
#define CYDEV_PHUB_TDMEM15_SIZE
#define CYDEV_CAN0_TX0_SIZE
#define CYDEV_USB_ARB_RW5_SIZE
#define CYDEV_PRTDSI_PRT5_BASE
#define CYDEV_ANAIF_WRK_DAC0_SIZE
#define CYDEV_USB_ARB_RW7_SIZE
#define CYDEV_CLKDIST_DCFG3_SIZE
#define CYDEV_UWRK_UWRK8_SIZE
#define CYDEV_PHUB_TDMEM85_SIZE
#define CYDEV_UCFG_B0_P1_U1_BASE
#define CYDEV_CLKDIST_DCFG1_BASE
#define CYDEV_MFGCFG_ANAIF_CMP3_BASE
#define CYDEV_USB_ARB_EP1_BASE
#define CYDEV_ANAIF_CFG_CMP1_SIZE
#define CYDEV_PHUB_TDMEM15_BASE
#define CYCLK_SRC_SEL_ILO
#define CYDEV_IO_PRT_PRT15_SIZE
#define CYDEV_EEPROM_ROW_SIZE
#define CYDEV_UCFG_B1_P5_SIZE
#define CYDEV_PHUB_TDMEM80_BASE
#define CYDEV_UCFG_B1_P2_U1_SIZE
#define CYDEV_UCFG_B0_P4_SIZE
#define CYDEV_UCFG_B0_P3_ROUTE_SIZE
#define CYDEV_CAN0_RX9_SIZE
#define CYDEV_UCFG_B0_P5_U0_BASE
#define CYDEV_ANAIF_CFG_SC1_SIZE
#define CYDEV_PHUB_TDMEM89_SIZE
#define CYDEV_ANAIF_RT_DAC3_SIZE
#define CYDEV_PHUB_TDMEM115_BASE
#define CYDEV_MFGCFG_SIZE
#define CYDEV_PHUB_CFGMEM10_BASE
#define CYDEV_PHUB_TDMEM10_SIZE
#define CYDEV_ANAIF_RT_OPAMP1_SIZE
#define CYDEV_PHUB_TDMEM17_SIZE
#define CYDEV_PHUB_TDMEM7_BASE
#define CYDEV_UCFG_B0_P7_U1_BASE
#define CYDEV_ANAIF_CFG_CAPSR_BASE
#define CYDEV_PHUB_CFGMEM13_SIZE
#define CYDEV_CLKDIST_DCFG0_SIZE
#define CYDEV_PHUB_TDMEM33_SIZE
#define CYDEV_UCFG_B1_P4_ROUTE_BASE
#define CYDEV_USB_ARB_EP4_BASE
#define CYDEV_PHUB_TDMEM93_BASE
#define CYDEV_ANAIF_CFG_SAR1_SIZE
#define CYDEV_PHUB_CFGMEM23_SIZE
#define CYDEV_MFGCFG_ILO_SIZE
#define CYDEV_UCFG_B0_P4_U0_SIZE
#define CYDEV_FLSHID_BASE
#define CYDEV_UCFG_B0_P3_U0_SIZE
#define CYDEV_CAN0_RX8_SIZE
#define CYDEV_ANAIF_RT_OPAMP0_BASE
#define CYDEV_PICU_STAT_PICU5_SIZE
#define CYDEV_PHUB_CH16_SIZE
#define CYDEV_CAN0_RX4_BASE
#define CYDEV_UCFG_B0_P7_ROUTE_BASE
#define CYDEV_PICU_SNAP_BASE
#define CYDEV_IO_PRT_PRT0_BASE
#define CYDEV_UCFG_DSI0_SIZE
#define CYDEV_SLOWCLK_BASE
#define CYDEV_PHUB_TDMEM127_BASE
#define CYDEV_PHUB_TDMEM11_BASE
#define CYDEV_PHUB_TDMEM42_SIZE
#define CYDEV_PRTDSI_PRT15_BASE
#define CYDEV_PHUB_TDMEM71_BASE
#define CYDEV_IO_PRT_SIZE
#define CYDEV_PRTDSI_PRT4_SIZE
#define CYDEV_ANAIF_CFG_LCDTMR_BASE
#define CYDEV_CAN0_TX7_BASE
#define CYDEV_PHUB_CFGMEM1_BASE
#define CYDEV_FASTCLK_IMO_BASE
#define CYDEV_PHUB_CFGMEM14_SIZE
#define CYDEV_USB_SIE_EP8_BASE
#define CYDEV_UCFG_B1_P3_U1_BASE
#define CYDEV_PHUB_TDMEM43_BASE
#define CYDEV_CLKDIST_DCFG4_BASE
#define CYDEV_PHUB_TDMEM87_BASE
#define CYDEV_PHUB_TDMEM57_BASE
#define CYDEV_IO_PC_PRT1_SIZE
#define CYDEV_PHUB_CFGMEM2_SIZE
#define CYDEV_PHUB_TDMEM93_SIZE
#define CYDEV_PICU_DISABLE_COR_PICU1_BASE
#define CYDEV_PHUB_TDMEM75_BASE
#define CYDEV_USB_ARB_EP2_SIZE
#define CYDEV_UCFG_B1_P4_U1_BASE
#define CYDEV_PHUB_CH22_SIZE
#define CYDEV_PHUB_TDMEM81_SIZE
#define CYDEV_SPC_DMM_MAP_SIZE
#define CYDEV_PHUB_TDMEM123_SIZE
#define CYDEV_PHUB_CFGMEM3_BASE
#define CYDEV_PHUB_TDMEM97_BASE
#define CYDEV_PHUB_CH20_BASE
#define CYDEV_SLOWCLK_SIZE
#define CYDEV_IO_DR_PRT5_SIZE
#define CYDEV_PHUB_TDMEM112_BASE
#define CYDEV_UCFG_B0_P5_SIZE
#define CYDEV_ANAIF_CFG_SAR0_BASE
#define CYDEV_UCFG_B0_P0_BASE
#define CYCLK_SRC_SEL_XTALK
#define CYDEV_PHUB_CH0_SIZE
#define CYDEV_IO_PS_PRT12_SIZE
#define CYDEV_IO_PC_PRT1_BASE
#define CYDEV_UCFG_B1_P3_U0_BASE
#define CYDEV_IO_PC_PRT4_BASE
#define CYDEV_IO_PS_PRT2_BASE
#define CYDEV_IO_PS_PRT4_BASE
#define CYDEV_CAN0_TX7_SIZE
#define CYDEV_UCFG_B1_P2_U0_SIZE
#define CYDEV_PHUB_TDMEM48_SIZE
#define CYDEV_USB_ARB_RW1_SIZE
#define CYDEV_CAN0_RX4_SIZE
#define CYDEV_UCFG_B1_P2_ROUTE_BASE
#define CYDEV_PHUB_CH3_BASE
#define CYDEV_PICU_INTTYPE_PICU15_BASE
#define CYDEV_UCFG_DSI3_SIZE
#define CYDEV_UCFG_B1_P2_U1_BASE
#define CYDEV_UCFG_B0_P6_BASE
#define CYDEV_PHUB_TDMEM120_SIZE
#define CYDEV_PICU_INTTYPE_PICU6_SIZE
#define CYDEV_UCFG_DSI4_BASE
#define CYDEV_PHUB_TDMEM69_SIZE
#define CYDEV_IO_PS_PRT6_SIZE
#define CYDEV_ANAIF_RT_SC3_BASE
#define CYDEV_PICU_INTTYPE_PICU4_BASE
#define CYDEV_PHUB_TDMEM13_SIZE
#define CYDEV_PICU_DISABLE_COR_PICU3_SIZE
#define CYDEV_FASTCLK_XMHZ_SIZE
#define CYDEV_IO_DR_PRT6_SIZE
#define CYDEV_PHUB_TDMEM78_BASE
#define CYDEV_PICU_STAT_PICU2_SIZE
#define CYDEV_PHUB_TDMEM100_BASE
#define CYDEV_MFGCFG_ANAIF_CMP2_BASE
#define CYDEV_ANAIF_CFG_LUT0_BASE
#define CYDEV_UCFG_B0_P0_U1_BASE
#define CYDEV_IO_PRT_PRT2_SIZE
#define CYDEV_PHUB_TDMEM24_BASE
#define CYDEV_PHUB_TDMEM62_SIZE
#define CYDEV_EXTMEM_SIZE
#define CYDEV_DFB0_DPB_SRAM_BASE
#define CYDEV_ANAIF_WRK_DAC1_BASE
#define CYDEV_CORE_DBG_SIZE
#define CYDEV_USB_SIE_EP3_SIZE
#define CYDEV_PHUB_TDMEM11_SIZE
#define CYDEV_IO_PRT_PRT1_BASE
#define CYDEV_FASTCLK_PLL_BASE
#define CYDEV_PHUB_TDMEM53_SIZE
#define CYDEV_PICU_SNAP_PICU5_BASE
#define CYDEV_PHUB_TDMEM124_SIZE
#define CYDEV_PHUB_TDMEM102_BASE
#define CYDEV_PHUB_TDMEM12_SIZE
#define CYDEV_USB_ARB_RW4_BASE
#define CYDEV_USB_SIE_EP4_SIZE
#define CYDEV_PHUB_TDMEM55_BASE
#define CYDEV_PHUB_CFGMEM0_SIZE
#define CYDEV_PHUB_CFGMEM4_SIZE
#define CYDEV_ANAIF_CFG_CMP1_BASE
#define CYDEV_PHUB_TDMEM125_BASE
#define CYDEV_ECC_SECTOR_SIZE
#define CYDEV_PRTDSI_PRT3_BASE
#define CYDEV_PICU_INTTYPE_PICU6_BASE
#define CYDEV_DFB0_CSA_SRAM_SIZE
#define CYDEV_IO_PS_PRT15_BASE
#define CYDEV_PICU_INTTYPE_PICU12_SIZE
#define CYDEV_ANAIF_CFG_SC0_BASE
#define CYDEV_PHUB_CH0_BASE
#define CYDEV_CAN0_RX1_BASE
#define CYDEV_PHUB_TDMEM59_BASE
#define CYDEV_MFGCFG_MLOGIC_SIZE
#define CYDEV_IO_PC_PRT0_BASE
#define CYDEV_PICU_SNAP_PICU12_BASE
#define CYDEV_UCFG_DSI8_SIZE
#define CYDEV_CLKDIST_ACFG1_SIZE
#define CYDEV_PHUB_TDMEM94_BASE
#define CYDEV_UCFG_DSI1_BASE
#define CYDEV_PHUB_TDMEM19_BASE
#define CYDEV_PHUB_TDMEM13_BASE
#define CYDEV_PHUB_TDMEM21_SIZE
#define CYDEV_PICU_STAT_PICU1_BASE
#define CYDEV_ANAIF_RT_SC1_BASE
#define CYDEV_ANAIF_WRK_DSM0_BASE
#define CYDEV_PHUB_TDMEM47_SIZE
#define CYDEV_PHUB_CFGMEM6_SIZE
#define CYDEV_UCFG_B0_P5_U1_BASE
#define CYDEV_ANAIF_CFG_SC3_BASE
#define CYDEV_PHUB_TDMEM112_SIZE
#define CYCLK_SRC_SEL_DSI_A
#define CYDEV_PHUB_TDMEM95_BASE
#define CYDEV_PICU_DISABLE_COR_PICU2_SIZE
#define CYDEV_ANAIF_RT_SC2_BASE
#define CYDEV_UCFG_B0_P7_SIZE
#define CYDEV_PHUB_TDMEM36_BASE
#define CYDEV_IO_PS_PRT6_BASE
#define CYDEV_UCFG_DSI1_SIZE
#define CYDEV_ANAIF_RT_CMP3_SIZE
#define CYDEV_PHUB_TDMEM53_BASE
#define CYDEV_PHUB_TDMEM44_SIZE
#define CYDEV_PICU_SNAP_PICU4_BASE
#define CYDEV_PHUB_TDMEM39_BASE
#define CYDEV_MFGCFG_ANAIF_CMP1_BASE
#define CYDEV_UCFG_DSI9_BASE
#define CYDEV_ANAIF_CFG_LCDTMR_SIZE
#define CYDEV_USB_ARB_RW8_BASE
#define CYDEV_PICU_STAT_PICU12_BASE
#define CYDEV_PHUB_TDMEM75_SIZE
#define CYDEV_PHUB_TDMEM90_BASE
#define CYDEV_CAN0_RX8_BASE
#define CYDEV_CLKDIST_DCFG5_SIZE
#define CYDEV_MFGCFG_MLOGIC_SEG_BASE
#define CYDEV_UWRK_UWRK16_CAT_B0_BASE
#define CYDEV_PHUB_CH19_BASE
#define CYDEV_PHUB_TDMEM36_SIZE
#define CYDEV_UCFG_B0_P1_ROUTE_SIZE
#define CYDEV_FLSECC_SIZE
#define CYDEV_PHUB_TDMEM58_BASE
#define CYDEV_PHUB_CH2_BASE
#define CYDEV_ANAIF_RT_SC3_SIZE
#define CYDEV_PHUB_TDMEM1_BASE
#define CYDEV_DFB0_CSB_SRAM_SIZE
#define CYDEV_PHUB_TDMEM77_BASE
#define CYDEV_PICU_INTTYPE_PICU5_BASE
#define CYDEV_USB_ARB_EP8_BASE
#define CYDEV_UCFG_B1_P3_U1_SIZE
#define CYDEV_UCFG_B0_P2_U1_BASE
#define CYDEV_CLKDIST_ACFG0_BASE
#define CYDEV_PHUB_TDMEM58_SIZE
#define CYDEV_PHUB_TDMEM2_BASE
#define CYDEV_PHUB_TDMEM80_SIZE
#define CYDEV_PHUB_TDMEM109_SIZE
#define CYDEV_PHUB_TDMEM124_BASE
#define CYDEV_CACHERAM_BASE
#define CYDEV_IO_DR_PRT5_BASE
#define CYDEV_IO_PC_PRT0_SIZE
#define CYDEV_USB_ARB_EP5_BASE
#define CYDEV_UCFG_DSI12_SIZE
#define CYDEV_MFGCFG_BASE
#define CYDEV_PHUB_TDMEM76_BASE
#define CYDEV_PHUB_TDMEM119_BASE
#define CYDEV_PHUB_CH12_SIZE
#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE
#define CYDEV_PHUB_CH13_BASE
#define CYDEV_PHUB_TDMEM7_SIZE
#define CYDEV_PICU_SNAP_PICU0_BASE
#define CYDEV_UCFG_B0_P7_BASE
#define CYDEV_PHUB_TDMEM18_BASE
#define CYDEV_UCFG_B0_P1_ROUTE_BASE
#define CYDEV_USB_SIE_EP4_BASE
#define CYDEV_PHUB_TDMEM21_BASE
#define CYDEV_PHUB_CFGMEM15_SIZE
#define CYDEV_PHUB_CFGMEM11_SIZE
#define CYDEV_USB_ARB_EP1_SIZE
#define CYDEV_MFGCFG_MLOGIC_SEG_SIZE
#define CYDEV_PRTDSI_PRT1_SIZE
#define CYDEV_PHUB_TDMEM14_SIZE
#define CYDEV_IO_PC_PRT15_BASE
#define CYDEV_UCFG_BCTL0_BASE
#define CYDEV_PHUB_TDMEM5_BASE
#define CYDEV_SPC_DMM_MAP_BASE
#define CYDEV_PICU_INTTYPE_PICU3_BASE
#define CYDEV_FLSHID_CUST_TABLES_BASE
#define CYDEV_PHUB_CFGMEM19_BASE
#define CYDEV_UWRK_UWRK16_DEF_BASE
#define CYDEV_UCFG_B1_P5_U1_SIZE
#define CYDEV_PHUB_TDMEM74_SIZE
#define CYDEV_IO_DR_PRT4_BASE
#define CYDEV_IO_PC_PRT15_SIZE
#define CYDEV_IO_PS_PRT1_BASE
#define CYDEV_PHUB_TDMEM77_SIZE
#define CYDEV_PHUB_TDMEM113_BASE
#define CYDEV_MFGCFG_ANAIF_SAR1_BASE
#define CYDEV_PHUB_TDMEM63_BASE
#define CYDEV_UCFG_B1_P3_ROUTE_BASE
#define CYDEV_ANAIF_RT_DAC0_SIZE
#define CYDEV_PM_STBY_BASE
#define CYDEV_PHUB_TDMEM101_BASE
#define CYDEV_UCFG_B1_P4_U0_SIZE
#define CYDEV_PHUB_CFGMEM13_BASE
#define CYDEV_PICU_DISABLE_COR_PICU5_SIZE
#define CYDEV_PHUB_TDMEM4_SIZE
#define CYDEV_ANAIF_CFG_CMP2_BASE
#define CYDEV_USB_ARB_EP2_BASE
#define CYDEV_USB_ARB_RW2_SIZE
#define CYDEV_DFB0_FSM_SRAM_SIZE
#define CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE
#define CYDEV_UCFG_B0_P0_U1_SIZE
#define CYDEV_PHUB_TDMEM106_BASE
#define CYDEV_MFGCFG_IMO_SIZE
#define CYDEV_ANAIF_RT_OPAMP3_SIZE
#define CYDEV_PHUB_TDMEM69_BASE
#define CYDEV_PHUB_TDMEM84_SIZE
#define CYDEV_PHUB_TDMEM111_SIZE
#define CYDEV_CORE_DBG_BASE
#define CYDEV_ANAIF_CFG_OPAMP0_BASE
#define CYDEV_PHUB_TDMEM116_SIZE
#define CYDEV_PHUB_CH9_BASE
#define CYDEV_PRTDSI_PRT3_SIZE
#define CYDEV_UWRK_UWRK16_DEF_SIZE
#define CYDEV_IO_PS_PRT5_BASE
#define CYDEV_CAN0_TX5_BASE
#define CYDEV_PHUB_TDMEM33_BASE
#define CYDEV_CAN0_RX9_BASE
#define CYDEV_UCFG_DSI5_SIZE
#define CYDEV_ANAIF_CFG_BG_BASE
#define CYDEV_DFB0_ACU_SRAM_SIZE
#define CYDEV_IO_PS_PRT1_SIZE
#define CYDEV_CAN0_RX15_BASE
#define CYDEV_DFB0_DPB_SRAM_SIZE
#define CYDEV_PHUB_TDMEM34_BASE
#define CYDEV_CAN0_RX14_SIZE
#define CYDEV_UCFG_B0_P6_U0_SIZE
#define CYDEV_IO_PS_PRT15_SIZE
#define CYDEV_UCFG_B0_P0_U0_BASE
#define CYDEV_UWRK_UWRK16_CAT_BASE
#define CYDEV_PHUB_TDMEM73_BASE
#define CYDEV_PHUB_TDMEM89_BASE
#define CYDEV_ANAIF_CFG_CMP0_SIZE
#define CYDEV_PICU_INTTYPE_PICU12_BASE
#define CYDEV_PHUB_TDMEM6_BASE
#define CYDEV_PM_ACT_BASE
#define CYDEV_PHUB_TDMEM52_BASE
#define CYDEV_PHUB_TDMEM41_BASE
#define CYDEV_MFGCFG_ANAIF_DAC1_BASE
#define CYDEV_UCFG_B0_P1_BASE
#define CYDEV_ANAIF_CFG_DAC1_BASE
#define CYDEV_ANAIF_CFG_DAC3_BASE
#define CYDEV_IO_DR_PRT15_BASE
#define CYDEV_IO_DR_PRT3_SIZE
#define CYDEV_PHUB_TDMEM52_SIZE
#define CYDEV_PHUB_CH5_SIZE
#define CYDEV_FASTCLK_BASE
#define CYDEV_PRTDSI_PRT0_BASE
#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE
#define CYDEV_ANAIF_CFG_SC1_BASE
#define CYDEV_PHUB_TDMEM125_SIZE
#define CYDEV_CAN0_RX14_BASE
#define CYDEV_PHUB_CH16_BASE
#define CYDEV_USB_SIE_EP6_SIZE
#define CYDEV_PHUB_TDMEM64_BASE
#define CYDEV_UCFG_DSI6_SIZE
#define CYDEV_PHUB_TDMEM37_SIZE
#define CYDEV_FLS_ROW_SIZE
#define CYDEV_FLSHID_SIZE
#define CYDEV_PICU_DISABLE_COR_SIZE
#define CYDEV_PICU_SNAP_PICU6_BASE
#define CYDEV_CLKDIST_DCFG5_BASE
#define CYDEV_IO_PRT_PRT4_BASE
#define CYDEV_UCFG_B1_P2_U0_BASE
#define CYDEV_CAN0_RX13_BASE
#define CYDEV_PHUB_TDMEM29_SIZE
#define CYCLK_SRC_SEL_CLK_SYNC_A
#define CYDEV_PICU_INTTYPE_PICU1_SIZE
#define CYDEV_USB_SIE_EP2_BASE
#define CYDEV_PHUB_TDMEM17_BASE
#define CYDEV_FASTCLK_SIZE
#define CYDEV_MFGCFG_ANAIF_DAC2_SIZE
#define CYDEV_UCFG_B1_P2_ROUTE_SIZE
#define CYDEV_PHUB_TDMEM123_BASE
#define CYDEV_PHUB_TDMEM104_BASE
#define CYDEV_MFGCFG_ANAIF_DAC0_BASE
#define CYDEV_UCFG_B1_SIZE
#define CYDEV_PHUB_TDMEM24_SIZE
#define CYDEV_MFGCFG_ANAIF_CMP2_SIZE
#define CYDEV_UCFG_B0_P2_U1_SIZE
#define CYDEV_ANAIF_RT_CMP3_BASE
#define CYDEV_PHUB_TDMEM29_BASE
#define CYDEV_PICU_DISABLE_COR_PICU3_BASE
#define CYDEV_ANAIF_CFG_SC0_SIZE
#define CYDEV_PHUB_CFGMEM17_SIZE
#define CYDEV_ANAIF_CFG_DSM0_BASE
#define CYDEV_UWRK_UWRK16_DEF_B1_BASE
#define CYDEV_CLKDIST_DCFG1_SIZE
#define CYDEV_UCFG_B0_P0_SIZE
#define CYDEV_PHUB_CH14_SIZE
#define CYDEV_USB_ARB_RW8_SIZE
#define CYCLK_SRC_SEL_PLL
#define CYDEV_PHUB_TDMEM66_SIZE
#define CYDEV_USB_ARB_EP7_BASE
#define CYDEV_UCFG_DSI3_BASE
#define CYDEV_IO_DR_PRT12_SIZE
#define CYDEV_PHUB_TDMEM22_BASE
#define CYDEV_IO_PC_PRT6_SIZE
#define CYDEV_UCFG_B0_P5_U0_SIZE
#define CYCLK_SRC_SEL_XTAL_MHZ
#define CYDEV_UCFG_B0_P5_ROUTE_SIZE
#define CYDEV_IO_PC_PRT3_BASE
#define CYDEV_MFGCFG_ANAIF_SAR0_SIZE
#define CYDEV_PICU_STAT_PICU1_SIZE
#define CYDEV_ANAIF_CFG_LUT1_BASE
#define CYDEV_IO_PS_PRT0_BASE
#define CYDEV_IO_PS_PRT4_SIZE
#define CYDEV_MFGCFG_ANAIF_DAC2_BASE
#define CYDEV_CLKDIST_DCFG3_BASE
#define CYDEV_ANAIF_RT_OPAMP2_SIZE
#define CYDEV_CLKDIST_ACFG1_BASE
#define CYDEV_PHUB_TDMEM31_SIZE
#define CYDEV_PHUB_TDMEM0_BASE
#define CYDEV_PM_ACT_SIZE
#define CYDEV_UWRK_UWRK16_CAT_B1_SIZE
#define CYDEV_MFGCFG_ANAIF_CMP0_SIZE
#define CYDEV_PHUB_TDMEM86_SIZE
#define CYDEV_USB_SIE_EP7_SIZE
#define CYDEV_UCFG_DSI7_BASE
#define CYDEV_PHUB_TDMEM111_BASE
#define CYDEV_PICU_SNAP_PICU2_BASE
#define CYDEV_UCFG_B1_P5_U1_BASE
#define CYDEV_PHUB_TDMEM35_BASE
#define CYDEV_ANAIF_CFG_LCDDAC_BASE
#define CYDEV_ANAIF_CFG_CAPSR_SIZE
#define CYDEV_UCFG_B0_P7_U1_SIZE
#define CYDEV_PHUB_TDMEM107_BASE
#define CYDEV_PHUB_CH15_BASE
#define CYDEV_PHUB_TDMEM115_SIZE
#define CYDEV_PHUB_TDMEM72_BASE
#define CYDEV_PICU_INTTYPE_PICU2_SIZE
#define CYDEV_PHUB_TDMEM23_BASE
#define CYDEV_PRTDSI_PRT0_SIZE
#define CYDEV_PHUB_CH18_SIZE
#define CYDEV_ANAIF_RT_SAR0_BASE
#define CYDEV_UWRK_UWRK16_DEF_B0_BASE
#define CYDEV_MFGCFG_ANAIF_SAR0_BASE
#define CYDEV_PHUB_TDMEM51_BASE
#define CYDEV_PHUB_TDMEM70_BASE
#define CYDEV_ANAIF_RT_SC0_SIZE
#define CYDEV_ANAIF_RT_OPAMP2_BASE
#define CYDEV_ANAIF_WRK_DSM0_SIZE
#define CYDEV_CAN0_RX11_SIZE
#define CYDEV_PHUB_TDMEM44_BASE
#define CYDEV_ANAIF_CFG_LCDDRV_BASE
#define CYDEV_IO_PC_PRT15_7_6_BASE
#define CYDEV_DFB0_FSM_SRAM_BASE
#define CYDEV_ANAIF_WRK_SC_BASE
#define CYDEV_PHUB_TDMEM59_SIZE
#define CYDEV_ANAIF_RT_CMP0_BASE
#define CYDEV_PICU_DISABLE_COR_PICU0_BASE
#define CYDEV_PM_AVAIL_BASE
#define CYDEV_CLKDIST_DCFG7_SIZE
#define CYDEV_ANAIF_CFG_SAR1_BASE
#define CYDEV_UCFG_B0_SIZE
#define CYDEV_UWRK_UWRK8_BASE
#define CYCLK_SRC_SEL_CLK_SYNC_D
#define CYDEV_MFGCFG_ANAIF_SIZE
#define CYDEV_CAN0_RX7_SIZE
#define CYDEV_ANAIF_CFG_DAC0_BASE
#define CYDEV_PHUB_CFGMEM14_BASE
#define CYDEV_PHUB_TDMEM60_SIZE
#define CYDEV_CAN0_RX15_SIZE
#define CYDEV_PHUB_TDMEM65_SIZE
#define CYDEV_PHUB_CFGMEM19_SIZE
#define CYDEV_PRTDSI_PRT2_SIZE
#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE
#define CYDEV_IO_PRT_PRT15_BASE
#define CYDEV_CAN0_RX6_SIZE
#define CYDEV_PM_AVAIL_SIZE
#define CYDEV_PHUB_TDMEM37_BASE
#define CYDEV_PHUB_CFGMEM18_BASE
#define CYDEV_PHUB_TDMEM114_BASE
#define CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE
#define CYDEV_DFB0_DPA_SRAM_SIZE
#define CYDEV_PHUB_TDMEM57_SIZE
#define CYDEV_UWRK_UWRK8_B1_SIZE
#define CYDEV_SLOWCLK_ILO_BASE
#define CYDEV_ANAIF_CFG_DAC2_BASE
#define CYDEV_PHUB_CH8_SIZE
#define CYDEV_PICU_DISABLE_COR_PICU15_BASE
#define CYDEV_PHUB_CH13_SIZE
#define CYDEV_ANAIF_RT_DFT_BASE
#define CYDEV_IO_PS_PRT12_BASE
#define CYDEV_CLKDIST_ACFG2_SIZE
#define CYDEV_PICU_DISABLE_COR_PICU12_BASE
#define CYDEV_MFGCFG_IMO_BASE
#define CYDEV_PHUB_CH10_BASE
#define CYDEV_PICU_INTTYPE_PICU1_BASE
#define CYDEV_ANAIF_CFG_OPAMP2_SIZE
#define CYDEV_IO_PC_PRT2_BASE
#define CYDEV_UCFG_B0_P3_U1_SIZE
#define CYDEV_CLKDIST_DCFG6_BASE
#define CYDEV_UCFG_B0_P6_ROUTE_BASE
#define CYDEV_PHUB_TDMEM79_BASE
#define CYDEV_PHUB_CFGMEM9_SIZE
#define CYDEV_IO_PRT_PRT4_SIZE
#define CYDEV_UCFG_B1_P5_BASE
#define CYDEV_PHUB_TDMEM40_SIZE
#define CYDEV_PICU_STAT_PICU4_SIZE
#define CYDEV_PHUB_TDMEM68_BASE
#define CYDEV_UCFG_B0_P2_ROUTE_SIZE
#define CYDEV_MFGCFG_ANAIF_OPAMP0_BASE
#define CYDEV_CLKDIST_DCFG7_BASE
#define CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE
#define CYDEV_PHUB_TDMEM108_SIZE
#define CYDEV_PRTDSI_PRT6_SIZE
#define CYDEV_ANAIF_CFG_OPAMP0_SIZE
#define CYDEV_ANAIF_WRK_SAR1_SIZE
#define CYDEV_USB_SIE_EP1_BASE
#define CYDEV_PHUB_TDMEM102_SIZE
#define CYDEV_CAN0_RX13_SIZE
#define CYDEV_SLOWCLK_X32_SIZE
#define CYDEV_UCFG_B0_P2_BASE
#define CYDEV_UCFG_B1_P2_SIZE
#define CYDEV_PHUB_CH7_BASE
#define CYDEV_PHUB_TDMEM61_SIZE
#define CYDEV_PHUB_TDMEM34_SIZE
#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE
#define CYDEV_PHUB_TDMEM25_BASE
#define CYDEV_USB_ARB_RW6_BASE
#define CYDEV_PHUB_TDMEM18_SIZE
#define CYDEV_PHUB_TDMEM14_BASE
#define CYDEV_PHUB_TDMEM9_BASE
#define CYDEV_PICU_SNAP_PICU4_SIZE
#define CYDEV_MFGCFG_X32_SIZE
#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE
#define CYDEV_UCFG_B0_P6_ROUTE_SIZE
#define CYDEV_UCFG_B0_P3_U1_BASE
#define CYDEV_PRTDSI_BASE
#define CYDEV_PHUB_TDMEM48_BASE
#define CYDEV_ANAIF_CFG_LPF0_SIZE
#define CYDEV_PHUB_TDMEM121_SIZE
#define CYDEV_PHUB_TDMEM88_SIZE
#define CYDEV_PHUB_TDMEM38_BASE
#define CYDEV_ANAIF_WRK_SARS_SIZE
#define CYDEV_PHUB_TDMEM98_SIZE
#define CYDEV_ANAIF_WRK_DAC0_BASE
#define CYDEV_ANAIF_RT_SC_SIZE
#define CYDEV_PHUB_TDMEM45_SIZE
#define CYDEV_PHUB_TDMEM118_BASE
#define CYDEV_UCFG_B0_P0_ROUTE_BASE
#define CYCLK_SRC_SEL_IMO
#define CYDEV_PHUB_CH21_SIZE
#define CYDEV_ANAIF_CFG_BASE
#define CYDEV_UWRK_UWRK16_DEF_B1_SIZE
#define CYDEV_FLSHID_MFG_CFG_SIZE
#define CYDEV_IO_DR_PRT15_SIZE
#define CYDEV_PHUB_TDMEM51_SIZE
#define CYDEV_USB_ARB_RW1_BASE
#define CYDEV_PHUB_TDMEM43_SIZE
#define CYDEV_PHUB_CFGMEM10_SIZE
#define CYDEV_PHUB_TDMEM121_BASE
#define CYDEV_PHUB_TDMEM41_SIZE
#define CYDEV_PHUB_TDMEM67_SIZE
#define CYDEV_PHUB_CH7_SIZE
#define CYDEV_USB_ARB_RW7_BASE
#define CYDEV_PRTDSI_SIZE
#define CYDEV_USB_ARB_RW3_BASE
#define CYDEV_PHUB_TDMEM118_SIZE
#define CYDEV_UCFG_B0_P7_U0_SIZE
#define CYDEV_DFB0_CSA_SRAM_BASE
#define CYDEV_PHUB_TDMEM84_BASE
#define CYCLK_SRC_SEL_XTAL_KHZ
#define CYDEV_PHUB_TDMEM97_SIZE
#define CYDEV_PHUB_CFGMEM9_BASE
#define CYDEV_UCFG_B0_P3_U0_BASE
#define CYDEV_USB_SIE_EP3_BASE
#define CYDEV_PICU_INTTYPE_SIZE
#define CYDEV_PHUB_TDMEM122_BASE
#define CYDEV_PHUB_TDMEM105_SIZE
#define CYDEV_EXTMEM_BASE
#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE
#define CYDEV_UCFG_B0_P3_BASE
#define CYDEV_UWRK_UWRK16_CAT_SIZE
#define CYDEV_ANAIF_CFG_LUT0_SIZE
#define CYDEV_ANAIF_RT_BUS_SIZE
#define CYDEV_IO_PS_PRT3_SIZE
#define CYDEV_UCFG_B1_P5_ROUTE_SIZE
#define CYDEV_PICU_STAT_SIZE
#define CYDEV_ANAIF_RT_BUS_BASE
#define CYDEV_PHUB_TDMEM85_BASE
#define CYDEV_ANAIF_CFG_OPAMP3_BASE
#define CYDEV_PHUB_TDMEM10_BASE
#define CYDEV_PICU_STAT_PICU15_BASE
#define CYDEV_IO_DR_PRT0_BASE
#define CYDEV_SLOWCLK_ILO_SIZE
#define CYDEV_UWRK_UWRK16_SIZE
#define CYDEV_PHUB_TDMEM94_SIZE
#define CYDEV_MFGCFG_XMHZ_BASE
#define CYDEV_PICU_DISABLE_COR_PICU5_BASE
#define CYDEV_UCFG_B0_P3_SIZE
#define CYDEV_PHUB_TDMEM50_SIZE
#define CYDEV_PM_STBY_SIZE
#define CYDEV_DFB0_DPA_SRAM_BASE
#define CYDEV_PICU_STAT_PICU0_BASE
#define CYDEV_ANAIF_CFG_PUMP_SIZE
#define CYDEV_ANAIF_WRK_CMP_SIZE
#define CYDEV_UCFG_B1_P4_BASE
#define CYDEV_UCFG_B0_P5_BASE
#define CYDEV_PRTDSI_PRT6_BASE
#define CYDEV_ANAIF_WRK_LUT_SIZE
#define CYDEV_PICU_DISABLE_COR_BASE
#define CYDEV_IO_PRT_PRT5_BASE
#define CYDEV_PICU_INTTYPE_PICU0_BASE
#define CYDEV_UCFG_BCTL1_SIZE
#define CYDEV_ANAIF_RT_DAC2_BASE
#define CYDEV_IO_PS_PRT3_BASE
#define CYDEV_PHUB_TDMEM73_SIZE
#define CYDEV_PHUB_TDMEM55_SIZE
#define CYDEV_ANAIF_RT_SIZE
#define CYDEV_PHUB_TDMEM56_BASE
#define CYDEV_ANAIF_CFG_CMP3_BASE
#define CYDEV_PICU_SNAP_PICU1_SIZE
#define CYDEV_ANAIF_RT_CMP1_BASE
#define CYDEV_PHUB_TDMEM28_SIZE
#define CYDEV_PHUB_CFGMEM8_SIZE
#define CYDEV_PHUB_TDMEM46_SIZE
#define CYDEV_PHUB_TDMEM27_SIZE
#define CYDEV_ANAIF_RT_CMP2_SIZE
#define CYDEV_PHUB_TDMEM38_SIZE
#define CYDEV_UCFG_B1_P2_BASE
#define CYDEV_IO_PC_PRT3_SIZE
#define CYDEV_IO_PC_PRT5_BASE
#define CYDEV_UCFG_B0_P5_ROUTE_BASE
#define CYDEV_PHUB_TDMEM103_BASE
#define CYDEV_PHUB_TDMEM66_BASE
#define CYDEV_CLKDIST_SIZE
#define CYDEV_PICU_DISABLE_COR_PICU4_SIZE
#define CYDEV_UCFG_B0_P6_SIZE
#define CYDEV_IO_PC_PRT4_SIZE
#define CYDEV_ANAIF_CFG_DAC1_SIZE
#define CYDEV_ANAIF_WRK_DAC1_SIZE
#define CYDEV_PHUB_TDMEM20_SIZE
#define CYDEV_USB_ARB_EP6_BASE
#define CYDEV_DFB0_ACU_SRAM_BASE
#define CYDEV_PHUB_CFGMEM6_BASE
#define CYDEV_CAN0_RX10_BASE
#define CYDEV_ANAIF_CFG_LUT3_SIZE
#define CYDEV_EEPROM_SECTOR_SIZE
#define CYDEV_CLKDIST_ACFG3_BASE
#define CYDEV_UWRK_UWRK16_DEF_B0_SIZE
#define CYDEV_USB_ARB_EP5_SIZE
#define CYDEV_CAN0_RX7_BASE
#define CYDEV_PHUB_CH17_SIZE
#define CYDEV_PHUB_CH9_SIZE
#define CYDEV_ANAIF_CFG_LCDDRV_SIZE
#define CYDEV_PHUB_CH18_BASE
#define CYDEV_PHUB_TDMEM4_BASE
#define CYDEV_MFGCFG_ANAIF_CMP1_SIZE
#define CYDEV_CAN0_CSR_SIZE
#define CYDEV_CAN0_RX5_BASE
#define CYDEV_ANAIF_CFG_DSM0_SIZE
#define CYDEV_PICU_SNAP_PICU_15_SIZE
#define CYDEV_UCFG_B0_P2_U0_SIZE
#define CYDEV_DFB0_CSB_SRAM_BASE
#define CYDEV_PHUB_TDMEM16_BASE
#define CYDEV_PHUB_TDMEM101_SIZE
#define CYDEV_CAN0_RX3_SIZE
#define CYDEV_PHUB_TDMEM87_SIZE
#define CYDEV_PHUB_TDMEM103_SIZE
#define CYDEV_PICU_STAT_BASE
#define CYDEV_USB_MEM_SIZE
#define CYDEV_PHUB_TDMEM88_BASE
#define CYDEV_CLKDIST_DCFG4_SIZE
#define CYDEV_PICU_INTTYPE_PICU5_SIZE
#define CYDEV_ANAIF_RT_DSM0_BASE
#define CYDEV_PHUB_TDMEM100_SIZE
#define CYDEV_PICU_SNAP_SIZE
#define CYDEV_PHUB_TDMEM98_BASE
#define CYDEV_IO_PC_PRT6_BASE
#define CYDEV_PHUB_CH11_BASE
#define CYDEV_PICU_SNAP_PICU3_SIZE
#define CYDEV_FLSECC_BASE
#define CYDEV_MFGCFG_ANAIF_DAC3_BASE
#define CYDEV_UCFG_B1_P5_U0_BASE
#define CYDEV_PHUB_CH1_SIZE
#define CYDEV_PHUB_TDMEM117_BASE
#define CYDEV_PHUB_TDMEM35_SIZE
#define CYDEV_PHUB_TDMEM95_SIZE
#define CYDEV_PHUB_TDMEM67_BASE
#define CYDEV_ANAIF_WRK_DAC3_SIZE
#define CYDEV_PHUB_CFGMEM20_SIZE
#define CYDEV_CLKDIST_BASE
#define CYDEV_ANAIF_WRK_SAR1_BASE
#define CYDEV_PICU_SNAP_PICU5_SIZE
#define CYDEV_ANAIF_WRK_SIZE
#define CYDEV_PHUB_CH23_BASE
#define CYDEV_MFGCFG_ANAIF_CMP3_SIZE
#define CYDEV_PHUB_CFGMEM12_BASE
#define CYDEV_PICU_SNAP_PICU3_BASE
#define CYDEV_PHUB_TDMEM120_BASE
#define CYDEV_PHUB_TDMEM92_SIZE
#define CYDEV_PWRSYS_BASE
#define CYDEV_ANAIF_CFG_CAPSL_BASE
#define CYDEV_PICU_DISABLE_COR_PICU6_BASE
#define CYDEV_PHUB_TDMEM122_SIZE
#define CYDEV_UCFG_DSI13_BASE
#define CYDEV_FLSHID_CUST_TABLES_SIZE
#define CYDEV_PHUB_CFGMEM3_SIZE
#define CYDEV_ANAIF_RT_OPAMP3_BASE
#define CYDEV_PHUB_CH20_SIZE
#define CYDEV_ROM_TABLE_BASE
#define CYDEV_PHUB_TDMEM90_SIZE
#define CYDEV_PHUB_TDMEM54_BASE
#define CYDEV_PHUB_CFGMEM22_SIZE
#define CYDEV_PHUB_TDMEM65_BASE
#define CYDEV_USB_ARB_EP8_SIZE
#define CYDEV_UCFG_DSI0_BASE
#define CYDEV_PHUB_TDMEM91_SIZE
#define CYDEV_ANAIF_CFG_LUT1_SIZE
#define CYDEV_PHUB_TDMEM108_BASE
#define CYDEV_ANAIF_CFG_LUT3_BASE
#define CYDEV_ANAIF_CFG_LPF0_BASE
#define CYDEV_USB_ARB_RW3_SIZE
#define CYDEV_PHUB_CFGMEM8_BASE
#define CYDEV_PHUB_CH11_SIZE
#define CYDEV_PHUB_TDMEM81_BASE
#define CYDEV_PHUB_CFGMEM7_BASE
#define CYDEV_UCFG_B1_P3_ROUTE_SIZE
#define CYDEV_PHUB_TDMEM45_BASE
#define CYDEV_FASTCLK_IMO_SIZE
#define CYDEV_PHUB_TDMEM107_SIZE
#define CYDEV_UCFG_BCTL0_SIZE
#define CYCLK_SRC_SEL_XTALM
#define CYDEV_PHUB_TDMEM27_BASE
#define CYDEV_IO_PRT_PRT12_SIZE
#define CYDEV_ANAIF_RT_SAR1_SIZE
#define CYDEV_USB_ARB_RW4_SIZE
#define CYDEV_USB_SIE_EP7_BASE
#define CYDEV_PHUB_CH22_BASE
#define CYDEV_ANAIF_RT_SC1_SIZE
#define CYDEV_CLKDIST_DCFG2_SIZE
#define CYDEV_PHUB_TDMEM54_SIZE
#define CYDEV_ANAIF_CFG_LUT2_BASE
#define CYDEV_PHUB_CFGMEM5_BASE
#define CYDEV_UCFG_B0_P1_U0_SIZE
#define CYDEV_IO_PS_PRT2_SIZE
#define CYDEV_PHUB_CH6_SIZE
#define CYDEV_PHUB_CH4_BASE
#define CYDEV_CAN0_TX4_SIZE
#define CYDEV_USB_ARB_RW6_SIZE
#define CYDEV_PICU_SNAP_PICU0_SIZE
#define CYDEV_PRTDSI_PRT12_BASE
#define CYDEV_PHUB_TDMEM0_SIZE
#define CYDEV_ANAIF_RT_SC0_BASE
#define CYDEV_IO_DR_PRT2_BASE
#define CYDEV_MFGCFG_ANAIF_DAC1_SIZE
#define CYDEV_ANAIF_CFG_CMP3_SIZE
#define CYDEV_PANTHER_BASE
#define CYDEV_PHUB_TDMEM50_BASE
#define CYDEV_PHUB_TDMEM22_SIZE
#define CYDEV_PHUB_CH6_BASE
#define CYDEV_CLKDIST_DCFG0_BASE
#define CYDEV_CLKDIST_DCFG2_BASE
#define CYDEV_IO_DR_PRT3_BASE
#define CYDEV_IO_PRT_PRT6_BASE
#define CYDEV_PHUB_TDMEM30_SIZE
#define CYDEV_PHUB_TDMEM79_SIZE
#define CYDEV_PHUB_TDMEM82_BASE
#define CYDEV_UCFG_DSI2_SIZE
#define CYDEV_PHUB_TDMEM110_BASE
#define CYDEV_CAN0_TX4_BASE
#define CYDEV_PHUB_TDMEM116_BASE
#define CYDEV_PHUB_TDMEM113_SIZE
#define CYDEV_PHUB_TDMEM32_BASE
#define CYDEV_ANAIF_RT_SAR0_SIZE
#define CYDEV_PHUB_TDMEM83_SIZE
#define CYDEV_ANAIF_WRK_CMP_BASE
#define CYDEV_PICU_STAT_PICU4_BASE
#define CYDEV_PHUB_CFGMEM0_BASE
#define CYDEV_CAN0_TX6_SIZE
#define CYDEV_ANAIF_CFG_LPF1_SIZE
#define CYDEV_PHUB_CFGMEM15_BASE
#define CYDEV_ECC_ROW_SIZE
#define CYDEV_ANAIF_CFG_OPAMP3_SIZE
#define CYDEV_USB_ARB_EP4_SIZE
#define CYDEV_IO_DR_PRT2_SIZE
#define CYDEV_UCFG_B1_P4_ROUTE_SIZE
#define CYDEV_USB_SIE_EP1_SIZE
#define CYDEV_UCFG_BCTL1_BASE
#define CYDEV_ANAIF_RT_SC2_SIZE
#define CYDEV_PANTHER_SIZE
#define CYDEV_ANAIF_CFG_MISC_BASE
#define CYDEV_PHUB_CFGMEM22_BASE
#define CYDEV_CAN0_TX0_BASE
#define CYDEV_PRTDSI_PRT4_BASE
#define CYDEV_PICU_STAT_PICU6_SIZE
#define CYDEV_PERIPH_BASE
#define CYDEV_ANAIF_RT_CMP2_BASE
#define CYDEV_MFGCFG_ANAIF_OPAMP2_BASE
#define CYDEV_UCFG_DSI13_SIZE
#define CYDEV_ANAIF_RT_DAC3_BASE
#define CYDEV_ANAIF_WRK_LUT_BASE
#define CYDEV_PHUB_CFGMEM16_SIZE
#define CYDEV_PHUB_TDMEM105_BASE
#define CYCLK_SRC_SEL_DSI_D
#define CYDEV_ANAIF_RT_DAC2_SIZE
#define CYDEV_ANAIF_RT_DAC0_BASE
#define CYDEV_PICU_SNAP_PICU6_SIZE
#define CYDEV_PHUB_CFGMEM20_BASE
#define CYDEV_PHUB_CH21_BASE
#define CYDEV_PICU_INTTYPE_PICU2_BASE
#define CYDEV_ANAIF_RT_SC_BASE
#define CYDEV_PHUB_TDMEM72_SIZE
#define CYDEV_ANAIF_CFG_OPAMP2_BASE
#define CYDEV_IO_PC_PRT15_7_6_SIZE
#define CYDEV_ROM_TABLE_SIZE
#define CYDEV_UCFG_B0_P4_ROUTE_BASE
#define CYDEV_USB_ARB_EP3_BASE
#define CYDEV_PHUB_TDMEM20_BASE
#define CYDEV_PHUB_CFGMEM21_SIZE
#define CYDEV_PHUB_CH17_BASE
#define CYDEV_UCFG_DSI9_SIZE
#define CYDEV_PHUB_CFGMEM5_SIZE
#define CYDEV_UCFG_B1_P5_ROUTE_BASE
#define CYDEV_ANAIF_RT_BASE
#define CYDEV_USB_SIE_EP2_SIZE
#define CYDEV_PHUB_TDMEM28_BASE
#define CYDEV_PHUB_TDMEM91_BASE
#define CYDEV_CAN0_RX0_SIZE
#define CYDEV_PHUB_CH2_SIZE
#define CYDEV_UCFG_DSI5_BASE
#define CYDEV_UCFG_B1_P4_U1_SIZE
#define CYDEV_PICU_SNAP_PICU1_BASE
#define CYDEV_CAN0_RX3_BASE
#define CYDEV_CAN0_RX2_SIZE
#define CYDEV_CAN0_RX11_BASE
#define CYDEV_USB_ARB_EP6_SIZE
#define CYDEV_PHUB_TDMEM127_SIZE
#define CYDEV_PICU_DISABLE_COR_PICU12_SIZE
#define CYDEV_ANAIF_RT_SAR1_BASE
#define CYDEV_PICU_STAT_PICU3_SIZE
#define CYDEV_PHUB_TDMEM47_BASE
#define CYDEV_IO_PRT_PRT2_BASE
#define CYDEV_ANAIF_RT_LCDDAC_SIZE
#define CYDEV_PHUB_TDMEM92_BASE
#define CYDEV_ANAIF_RT_OPAMP1_BASE
#define CYDEV_IO_PS_PRT0_SIZE
#define CYDEV_PHUB_TDMEM78_SIZE
#define CYCLK_SRC_SEL_SYNC_DIG
#define CYDEV_PHUB_TDMEM3_SIZE
#define CYDEV_PHUB_CH15_SIZE
#define CYDEV_UCFG_DSI4_SIZE
#define CYDEV_ANAIF_RT_DAC1_BASE
#define CYDEV_UCFG_B0_P6_U1_SIZE
#define CYDEV_ANAIF_RT_CMP1_SIZE
#define CYDEV_CAN0_TX3_BASE
#define CYDEV_UCFG_B0_P4_U1_SIZE
#define CYDEV_ANAIF_CFG_SC2_BASE
#define CYDEV_UCFG_B0_P6_U1_BASE
#define CYDEV_IO_PRT_PRT1_SIZE
#define CYDEV_PHUB_CFGMEM23_BASE
#define CYDEV_UCFG_B0_BASE
#define CYDEV_UCFG_B1_P3_U0_SIZE
#define CYDEV_UCFG_B1_P4_SIZE
#define CYDEV_PHUB_TDMEM117_SIZE
#define CYDEV_PHUB_TDMEM96_BASE
#define CYDEV_CACHERAM_SIZE
#define CYDEV_PHUB_CFGMEM18_SIZE
#define CYDEV_PICU_INTTYPE_PICU3_SIZE
#define CYDEV_IO_PS_PRT5_SIZE
#define CYDEV_PHUB_CH12_BASE
#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE
#define CYDEV_IO_PC_PRT12_SIZE
#define CYDEV_ANAIF_CFG_SIZE
#define CYDEV_PHUB_TDMEM46_BASE
#define CYDEV_PHUB_TDMEM74_BASE
#define CYDEV_UCFG_B1_P5_U0_SIZE
#define CYDEV_PICU_DISABLE_COR_PICU6_SIZE
#define CYDEV_ANAIF_CFG_CMP0_BASE
#define CYDEV_UWRK_UWRK16_CAT_B0_SIZE
#define CYDEV_PHUB_TDMEM110_SIZE
#define CYDEV_UCFG_B0_P4_U1_BASE
#define CYDEV_CLKDIST_DCFG6_SIZE
#define CYDEV_SLOWCLK_X32_BASE
#define CYDEV_IO_DR_PRT12_BASE
#define CYDEV_MFGCFG_PWRSYS_SIZE
#define CYDEV_PICU_INTTYPE_BASE
#define CYDEV_PHUB_TDMEM64_SIZE
#define CYDEV_PHUB_TDMEM106_SIZE
#define CYDEV_MFGCFG_X32_BASE
#define CYDEV_ANAIF_RT_LCDDAC_BASE
#define CYDEV_CAN0_RX12_BASE
#define CYDEV_MFGCFG_PWRSYS_BASE
#define CYDEV_PHUB_CFGMEM16_BASE
#define CYDEV_PHUB_TDMEM99_SIZE
#define CYDEV_PHUB_CH4_SIZE
#define CYDEV_USB_ARB_RW2_BASE
#define CYDEV_PHUB_TDMEM61_BASE
#define CYDEV_USB_ARB_RW5_BASE
#define CYDEV_PHUB_TDMEM42_BASE
#define CYDEV_PHUB_CH10_SIZE
#define CYDEV_ANAIF_CFG_LCDDAC_SIZE
#define CYDEV_PICU_INTTYPE_PICU0_SIZE
#define CYDEV_UWRK_UWRK16_CAT_B1_BASE
#define CYDEV_PICU_DISABLE_COR_PICU0_SIZE
#define CYDEV_PHUB_CH14_BASE
#define CYDEV_PICU_DISABLE_COR_PICU15_SIZE
#define CYDEV_PHUB_TDMEM56_SIZE
#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE
#define CYDEV_IO_DR_PRT0_SIZE
#define CYDEV_ANAIF_WRK_SAR0_BASE
#define CYDEV_MFGCFG_ILO_BASE
#define CYDEV_PWRSYS_SIZE
#define CYDEV_MFGCFG_ANAIF_SAR1_SIZE
#define CYDEV_ANAIF_CFG_BG_SIZE
#define CYDEV_PICU_SNAP_PICU_15_BASE
#define CYDEV_PICU_INTTYPE_PICU15_SIZE
#define CYDEV_PHUB_CFGMEM12_SIZE
#define CYDEV_PHUB_TDMEM76_SIZE
#define CYDEV_ANAIF_CFG_SC3_SIZE
#define CYDEV_USB_SIE_EP5_SIZE
#define CYDEV_FLSHID_MFG_CFG_BASE
#define CYDEV_USB_SIE_EP6_BASE
#define CYDEV_CAN0_CSR_BASE
#define CYDEV_ANAIF_RT_OPAMP0_SIZE
#define CYDEV_PRTDSI_PRT1_BASE
#define CYDEV_PHUB_TDMEM49_BASE
#define CYDEV_PHUB_CFGMEM4_BASE
#define CYDEV_UWRK_UWRK8_B0_SIZE
#define CYDEV_PHUB_TDMEM39_SIZE
#define CYDEV_CLKDIST_ACFG0_SIZE
#define CYDEV_PICU_SNAP_PICU12_SIZE
#define CYDEV_UCFG_B1_P4_U0_BASE
#define CYDEV_ANAIF_RT_DSM0_SIZE
#define CYDEV_PHUB_CFGMEM7_SIZE
#define CYDEV_PICU_INTTYPE_PICU4_SIZE
#define CYDEV_ANAIF_CFG_LUT2_SIZE
#define CYDEV_USB_SIE_EP8_SIZE
#define CYDEV_PHUB_TDMEM25_SIZE
#define CYDEV_USB_ARB_EP7_SIZE
#define CYDEV_ANAIF_WRK_DAC3_BASE
#define CYDEV_IO_PRT_PRT12_BASE
#define CYDEV_PHUB_CH8_BASE
#define CYDEV_PICU_DISABLE_COR_PICU1_SIZE
#define CYDEV_UCFG_DSI6_BASE
#define CYDEV_CAN0_RX10_SIZE
#define CYDEV_PHUB_TDMEM63_SIZE
#define CYDEV_UCFG_B0_P2_U0_BASE
#define CYDEV_ANAIF_CFG_MISC_SIZE
#define CYDEV_ANAIF_WRK_DAC2_BASE
#define CYDEV_MFGCFG_MLOGIC_BASE
#define CYDEV_CAN0_RX0_BASE
#define CYDEV_PHUB_TDMEM71_SIZE
#define CYDEV_PHUB_TDMEM70_SIZE
#define CYDEV_PHUB_TDMEM49_SIZE
#define CYDEV_PHUB_TDMEM26_BASE
#define CYDEV_IO_PRT_PRT3_BASE
#define CYDEV_PHUB_CFGMEM1_SIZE
#define CYDEV_UCFG_DSI7_SIZE
#define CYDEV_PHUB_TDMEM114_SIZE
#define CYDEV_FLS_SECTOR_SIZE
#define CYDEV_UCFG_DSI8_BASE
#define CYDEV_UCFG_DSI2_BASE
#define CYDEV_PHUB_TDMEM32_SIZE
#define CYDEV_ANAIF_WRK_DAC2_SIZE
#define CYDEV_CAN0_TX3_SIZE
#define CYDEV_ANAIF_WRK_BASE
#define CYDEV_UCFG_B1_P3_SIZE
#define CYDEV_PHUB_TDMEM16_SIZE
#define CYDEV_MFGCFG_ANAIF_BASE
#define CYDEV_ANAIF_RT_CMP0_SIZE
#define CYDEV_UCFG_B0_P7_U0_BASE
#define CYDEV_PHUB_TDMEM126_BASE
#define CYDEV_UCFG_B0_P1_U0_BASE
#define CYDEV_ANAIF_CFG_OPAMP1_BASE
#define CYDEV_PHUB_TDMEM109_BASE
#define CYDEV_PRTDSI_PRT15_SIZE
#define CYDEV_USB_ARB_EP3_SIZE
#define CYDEV_ANAIF_CFG_CAPSL_SIZE
#define CYDEV_PHUB_CH5_BASE
#define CYDEV_ANAIF_CFG_LPF1_BASE
#define CYDEV_IO_PRT_PRT0_SIZE
#define CYDEV_UCFG_B0_P0_U0_SIZE
#define CYDEV_UCFG_B1_BASE
#define CYDEV_IO_PC_PRT2_SIZE
#define CYDEV_UCFG_B0_P4_BASE
#define CYDEV_PHUB_CFGMEM21_BASE
#define CYDEV_PHUB_TDMEM9_SIZE
#define CYDEV_CAN0_TX1_BASE
#define CYDEV_UCFG_B0_P1_U1_SIZE
#define CYDEV_PICU_STAT_PICU6_BASE
#define CYDEV_UCFG_B1_P3_BASE
#define CYDEV_IO_DR_PRT4_SIZE
#define CYDEV_ANAIF_RT_DAC1_SIZE
#define CYDEV_MFGCFG_ANAIF_OPAMP1_BASE
#define CYDEV_IO_PRT_PRT3_SIZE
#define CYDEV_PICU_DISABLE_COR_PICU2_BASE
#define CYDEV_IO_PC_PRT12_BASE
#define CYDEV_PHUB_TDMEM96_SIZE
#define CYDEV_ANAIF_CFG_DAC2_SIZE
#define CYDEV_PHUB_TDMEM23_SIZE
#define CYDEV_PICU_DISABLE_COR_PICU4_BASE
#define CYDEV_ANAIF_CFG_SAR0_SIZE
#define CYDEV_UCFG_B0_P6_U0_BASE
#define CYDEV_UCFG_B0_P4_ROUTE_SIZE
#define CYDEV_MFGCFG_ANAIF_OPAMP3_BASE
#define CYDEV_PHUB_CFGMEM11_BASE
#define CYDEV_PHUB_CH3_SIZE
#define CYDEV_UWRK_UWRK8_B1_BASE
#define CYDEV_ANAIF_WRK_SARS_BASE
#define CYDEV_CAN0_TX6_BASE
#define CYDEV_PICU_STAT_PICU0_SIZE
#define CYDEV_PHUB_TDMEM68_SIZE
#define CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE
#define CYDEV_IO_DR_PRT6_BASE
#define CYDEV_PICU_STAT_PICU2_BASE
#define CYDEV_CAN0_TX1_SIZE
#define CYDEV_ANAIF_RT_DFT_SIZE
#define CYDEV_CAN0_TX2_BASE
#define CYDEV_PHUB_TDMEM1_SIZE
#define CYDEV_PRTDSI_PRT12_SIZE
#define CYDEV_PHUB_CH1_BASE
#define CYDEV_USB_MEM_BASE
#define CYDEV_UCFG_B0_P7_ROUTE_SIZE
#define CYDEV_ANAIF_CFG_OPAMP1_SIZE
#define CYDEV_MFGCFG_ANAIF_DAC0_SIZE
#define CYDEV_PHUB_TDMEM5_SIZE
#define CYDEV_ANAIF_CFG_CMP2_SIZE
#define CYDEV_PHUB_CFGMEM2_BASE
#define CYDEV_USB_SIE_EP5_BASE
#define CYDEV_PHUB_TDMEM60_BASE
#define CYDEV_CAN0_TX5_SIZE
#define CYDEV_PHUB_CH19_SIZE
#define CYDEV_PHUB_TDMEM26_SIZE
#define CYDEV_PHUB_TDMEM119_SIZE
#define CYDEV_PHUB_TDMEM104_SIZE
#define CYDEV_UCFG_B0_P2_SIZE
#define CYDEV_IO_PRT_PRT5_SIZE
#define CYDEV_UCFG_B0_P3_ROUTE_BASE
#define CYDEV_ANAIF_CFG_DAC0_SIZE
#define CYDEV_PRTDSI_PRT5_SIZE
#define CYDEV_FASTCLK_PLL_SIZE
#define CYDEV_UCFG_B0_P5_U1_SIZE
#define CYDEV_PRTDSI_PRT2_BASE
#define CYDEV_ANAIF_CFG_PUMP_BASE
#define CYDEV_IO_PRT_PRT6_SIZE
#define CYDEV_ANAIF_CFG_SC2_SIZE
#define CYDEV_PHUB_TDMEM3_BASE
#define CYREG_B0_UDB00_ST
#define CYREG_B0_P0_U1_DCFG5
#define CYREG_PICU12_DISABLE_COR
#define CYREG_B0_P1_U1_CFG9
#define CYREG_B0_P1_U0_CFG23
#define CYREG_B1_P5_U0_PLD_IT4
#define CYREG_DMA_SRAM64K_MSIZE
#define CYREG_B0_P4_U0_PLD_IT1
#define CYREG_PHUB_TDMEM21_ORIG_TD0
#define CYREG_PHUB_TDMEM99_ORIG_TD1
#define CYREG_B0_UDB04_05_F0
#define CYREG_PM_WAKEUP_CFG0
#define CYREG_B1_UDB08_09_D1
#define CYREG_B0_P7_U0_DCFG2
#define CYREG_B1_P4_U0_CFG25
#define CYREG_B0_P2_U0_CFG31
#define CYREG_B1_P4_U0_CFG14
#define CYREG_B1_P3_U0_DCFG4
#define CYREG_B0_P5_U1_CFG11
#define CYREG_PRT6_DBL_SYNC_IN
#define CYREG_FLSHID_CUST_TABLES_X_LOC
#define CYREG_B0_P4_U0_DCFG6
#define CYREG_B0_P3_U0_CFG2
#define CYREG_B0_P2_U1_PLD_IT9
#define CYREG_B0_P6_U1_CFG22
#define CYREG_B0_UDB03_04_CTL
#define CYREG_B1_P4_U0_DCFG0
#define CYREG_B0_P1_U1_PLD_IT4
#define CYREG_IO_PC_PRT15_PC3
#define CYREG_B1_UDB10_11_A0
#define CYREG_SLOWCLK_ILO_CR1
#define CYREG_I2C_TMOUT_SR
#define CYREG_USB_SIE_EP3_CR0
#define CYREG_B1_UDB07_F1
#define CYREG_B0_P6_U0_CFG18
#define CYREG_B0_P0_U0_PLD_IT3
#define CYREG_B1_P3_U1_PLD_IT4
#define CYREG_B0_P7_U1_CFG5
#define CYREG_PM_STBY_CFG1
#define CYREG_DMA_SRAM32K_MBASE
#define CYREG_B0_UDB07_08_ACTL
#define CYREG_B0_UDB08_09_A0
#define CYREG_B1_P5_U0_CFG3
#define CYREG_B1_UDB06_07_MC
#define CYREG_B0_P1_U1_CFG12
#define CYREG_PRT6_LCD_COM_SEG
#define CYREG_B0_P4_U0_PLD_IT4
#define CYREG_CAN0_TX5_DH
#define CYREG_PHUB_TDMEM94_ORIG_TD0
#define CYREG_NPUMP_DSM_TR0
#define CYREG_B1_UDB06_07_A1
#define CYREG_PRT0_SYNC_OUT
#define CYREG_B0_P2_U1_PLD_IT8
#define CYREG_USB_ARB_EP7_INT_EN
#define CYREG_B1_P4_U0_CFG21
#define CYREG_PHUB_CH20_BASIC_STATUS
#define CYREG_PHUB_CH18_ACTION
#define CYREG_B0_P5_U1_CFG1
#define CYREG_B0_P5_U0_PLD_ORT2
#define CYREG_B0_P2_U1_PLD_IT1
#define CYREG_B0_P3_U0_DCFG5
#define CYREG_B0_P5_U1_MC_CFG_CEN_CONST
#define CYREG_ROM_TABLE_PID4
#define CYREG_PHUB_CH0_ACTION
#define CYREG_PRT0_CAPS_SEL
#define CYREG_B0_UDB06_D0
#define CYREG_B1_UDB04_05_F1
#define CYREG_B0_UDB05_MSK
#define CYREG_PHUB_TDMEM32_ORIG_TD1
#define CYREG_ETM_ITATBCTR2
#define CYREG_B1_P4_U0_CFG11
#define CYREG_B0_P6_U1_CFG29
#define CYREG_FLSHID_CUST_TABLES_CMP3_TR1_HS
#define CYREG_PHUB_TDMEM103_ORIG_TD1
#define CYREG_B0_P3_U0_CFG10
#define CYREG_CAN0_RX12_ACRD
#define CYREG_B1_UDB06_07_D1
#define CYREG_B1_P4_U0_PLD_IT1
#define CYREG_B1_P2_U0_CFG29
#define CYREG_B0_P2_U0_CFG12
#define CYREG_B0_P6_U1_CFG6
#define CYREG_B0_P7_U0_MC_CFG_XORFB
#define CYREG_B0_UDB01_02_D0
#define CYREG_FLSHID_CUST_TABLES_DAC2_M3
#define CYREG_B0_UDB05_F0
#define CYREG_MLOGIC_DMPSTR
#define CYREG_USB_ARB_RW7_RA_MSB
#define CYREG_B1_UDB05_06_F1
#define CYREG_B0_UDB00_D1
#define CYREG_B0_P6_U1_MC_CFG_XORFB
#define CYREG_PM_ACT_CFG9
#define CYREG_FLSHID_CUST_TABLES_IMO_80MHZ
#define CYREG_PICU6_INTTYPE4
#define CYREG_B0_UDB04_MSK
#define CYREG_B1_UDB05_CTL
#define CYREG_B1_P4_U0_CFG12
#define CYREG_PHUB_TDMEM118_ORIG_TD1
#define CYREG_B0_P3_U1_CFG11
#define CYREG_B0_P5_U1_PLD_IT1
#define CYREG_B0_P4_U0_CFG25
#define CYREG_PM_AVAIL_CR0
#define CYREG_B0_P6_U1_CFG24
#define CYREG_BCTL0_BANK_CTL
#define CYREG_B1_UDB10_ST_CTL
#define CYREG_B1_UDB10_ACTL
#define CYREG_B0_P3_U1_CFG1
#define CYREG_PM_ACT_CFG2
#define CYREG_PHUB_TDMEM12_ORIG_TD1
#define CYREG_B0_P7_U1_CFG30
#define CYREG_B0_P5_U1_PLD_IT7
#define CYREG_PRT1_DBL_SYNC_IN
#define CYREG_CAN0_TX7_DL
#define CYREG_PHUB_CH12_ACTION
#define CYREG_USB_ARB_RW7_WA_MSB
#define CYREG_B0_UDB05_MSK_ACTL
#define CYREG_PHUB_TDMEM21_ORIG_TD1
#define CYREG_B0_P6_U0_PLD_ORT2
#define CYREG_B0_P6_U1_CFG0
#define CYREG_B0_UDB01_CTL
#define CYREG_USB_DYN_RECONFIG
#define CYREG_B0_P0_U0_CFG30
#define CYREG_B0_UDB09_MSK
#define CYREG_B0_UDB03_04_F0
#define CYREG_B0_UDB09_10_D0
#define CYREG_B0_P2_U0_CFG14
#define CYREG_BCTL1_MBCLK_EN
#define CYREG_B1_P5_U1_CFG24
#define CYREG_B0_P7_U0_CFG26
#define CYREG_B1_P2_U1_CFG10
#define CYREG_CAN0_RX1_ACR
#define CYREG_B0_P1_U0_CFG26
#define CYREG_B1_UDB11_CTL
#define CYREG_P3BA_EXP_DATA2
#define CYREG_PHUB_TDMEM71_ORIG_TD1
#define CYREG_B0_UDB11_12_MC
#define CYREG_B0_P6_U0_CFG31
#define CYREG_PHUB_TDMEM53_ORIG_TD0
#define CYREG_B0_P4_U1_PLD_IT3
#define CYREG_B0_P3_U0_PLD_IT5
#define CYREG_B0_P1_U1_CFG3
#define CYREG_B0_UDB14_A0
#define CYREG_B0_P3_U1_CFG8
#define CYREG_PRT4_OE_SEL0
#define CYREG_PHUB_TDMEM95_ORIG_TD0
#define CYREG_SFR_GPIO3_SEL
#define CYREG_PHUB_TDMEM122_ORIG_TD1
#define CYREG_B1_P2_U0_CFG7
#define CYREG_B0_P0_U1_CFG0
#define CYREG_BCTL1_DCLK_EN3
#define CYREG_B0_UDB01_02_D1
#define CYREG_IO_PC_PRT15_7_6_PC0
#define CYREG_B1_UDB05_MSK
#define CYREG_B0_UDB06_MSK
#define CYREG_USB_SIE_EP3_CNT0
#define CYREG_B0_UDB12_13_MC
#define CYREG_B0_P5_U0_CFG28
#define CYREG_B0_UDB02_ST
#define CYREG_CAN0_TX6_DH
#define CYREG_B0_P6_U0_PLD_ORT1
#define CYREG_B0_UDB11_CTL
#define CYREG_USB_EP0_DR3
#define CYREG_B0_UDB01_D0_D1
#define CYREG_OPAMP2_RSVD
#define CYREG_SRAM_DATA32K_MSIZE
#define CYREG_B0_P0_U0_PLD_IT5
#define CYREG_B0_P3_U1_PLD_IT6
#define CYREG_B0_P6_U1_PLD_IT5
#define CYREG_PHUB_CH20_ACTION
#define CYREG_FLSHID_CUST_TABLES_DAC2_M8
#define CYREG_PHUB_TDMEM49_ORIG_TD1
#define CYREG_PHUB_TDMEM106_ORIG_TD1
#define CYREG_PHUB_TDMEM0_ORIG_TD0
#define CYREG_B0_UDB06_D1
#define CYREG_B1_P5_U0_CFG12
#define CYREG_B0_UDB13_D0_D1
#define CYREG_P3BA_EXP_DATA1
#define CYREG_B0_P4_U1_PLD_ORT2
#define CYREG_DWT_FUNCTION_1
#define CYREG_EE_DATA_MBASE
#define CYREG_B1_P3_U1_DCFG4
#define CYREG_B0_P5_U0_CFG3
#define CYREG_FLSHID_CUST_TABLES_IMO_3MHZ
#define CYREG_DFB0_DMA_CTRL
#define CYREG_B0_UDB11_A1
#define CYREG_B1_P5_U1_PLD_IT11
#define CYREG_PRT6_CAPS_SEL
#define CYREG_B1_P5_U0_PLD_ORT0
#define CYREG_PHUB_CFGMEM17_CFG0
#define CYREG_B0_P3_U1_DCFG4
#define CYREG_B1_P3_U0_PLD_ORT0
#define CYREG_B1_P4_U0_DCFG5
#define CYREG_B0_P5_U0_PLD_IT8
#define CYREG_B1_P2_U0_PLD_IT5
#define CYREG_B1_P3_U0_PLD_IT4
#define CYREG_PHUB_TDMEM37_ORIG_TD1
#define CYREG_B0_P0_U0_CFG4
#define CYREG_B0_P5_U1_PLD_IT3
#define CYREG_B0_UDB05_D0_D1
#define CYREG_B0_UDB01_D1
#define CYREG_PHUB_CFGMEM22_CFG1
#define CYREG_B0_UDB11_A0_A1
#define CYREG_B1_P2_U0_DCFG2
#define CYREG_PHUB_TDMEM112_ORIG_TD1
#define CYREG_PRT15_BIT_MASK
#define CYREG_SPC_FM_EE_WAKE_CNT
#define CYREG_FLSHID_CUST_TABLES_DEC_M7
#define CYREG_OPAMP1_RSVD
#define CYREG_B0_P2_U1_DCFG5
#define CYREG_PRT1_CAPS_SEL
#define CYREG_B0_P6_U1_CFG16
#define CYREG_EMIF_NO_UDB
#define CYREG_B1_P4_U0_CFG29
#define CYREG_B0_P0_U1_PLD_ORT1
#define CYREG_B1_UDB04_D0
#define CYREG_B1_P4_U1_MC_CFG_CEN_CONST
#define CYREG_B0_UDB13_14_ACTL
#define CYREG_B0_P3_U0_PLD_IT10
#define CYREG_PHUB_TDMEM96_ORIG_TD1
#define CYREG_SRAM_DATA_MBASE
#define CYREG_B0_P2_U0_PLD_IT10
#define CYREG_PICU15_DISABLE_COR
#define CYREG_CAN0_RX12_ACR
#define CYREG_B0_P3_U1_CFG14
#define CYREG_TPIU_TRIGGER
#define CYREG_B0_UDB15_D0
#define CYREG_B0_P5_U1_CFG21
#define CYREG_B1_P2_U0_PLD_ORT1
#define CYREG_PRT4_PS_ALIAS
#define CYREG_B0_P5_U1_CFG20
#define CYREG_B0_P4_U0_CFG12
#define CYREG_B0_P4_U0_CFG27
#define CYREG_B0_P1_U0_PLD_IT7
#define CYREG_B1_P2_U0_CFG28
#define CYREG_B0_P2_U0_DCFG2
#define CYREG_B1_P4_U0_CFG4
#define CYREG_DAC1_STROBE
#define CYREG_NVIC_CLRENA0
#define CYREG_PHUB_TDMEM78_ORIG_TD0
#define CYREG_PRT0_DBL_SYNC_IN
#define CYREG_CLKDIST_DMASK
#define CYREG_B0_P5_U0_CFG31
#define CYREG_PHUB_TDMEM123_ORIG_TD1
#define CYREG_B0_P2_U1_CFG19
#define CYREG_B1_UDB10_MC_00
#define CYREG_USB_ARB_EP3_SR
#define CYREG_FLSHID_RSVD_MSIZE
#define CYREG_B1_P3_U0_CFG3
#define CYREG_USB_EP0_DR7
#define CYREG_USB_ARB_EP1_SR
#define CYREG_CAN0_RX9_CMD
#define CYREG_B0_UDB05_06_D1
#define CYREG_B1_P5_U0_CFG7
#define CYREG_B1_P5_U1_PLD_IT5
#define CYREG_B0_UDB04_D1
#define CYREG_FLSECC_DATA_MBASE
#define CYREG_B0_UDB08_09_MC
#define CYREG_SLOWCLK_X32_CFG
#define CYREG_B0_P4_U0_PLD_IT11
#define CYREG_CACHE_ECC_ERR
#define CYREG_USB_ARB_RW5_WA
#define CYREG_B0_P0_U0_MC_CFG_CEN_CONST
#define CYREG_B0_P1_U1_MC_CFG_CEN_CONST
#define CYREG_B1_P5_U0_DCFG7
#define CYREG_B0_P5_U1_CFG13
#define CYREG_B0_P6_U0_CFG12
#define CYREG_B1_UDB09_ACTL
#define CYREG_B1_P4_U0_PLD_IT10
#define CYREG_PHUB_TDMEM41_ORIG_TD1
#define CYREG_B1_P4_U1_CFG5
#define CYREG_B1_UDB05_06_ST
#define CYREG_B0_P6_U1_CFG27
#define CYREG_B1_P3_U1_PLD_IT3
#define CYREG_B0_P4_U1_CFG18
#define CYREG_FLSHID_MFG_CFG_CMP2_TR1
#define CYREG_PHUB_TDMEM94_ORIG_TD1
#define CYREG_PRT5_OUT_SEL1
#define CYREG_B0_UDB01_02_A0
#define CYREG_B0_P5_U1_CFG27
#define CYREG_CLKDIST_DCFG2_CFG2
#define CYREG_B0_P5_U1_CFG26
#define CYREG_B1_P5_U0_CFG21
#define CYREG_CAN0_RX3_DH
#define CYREG_TPIU_SUPPORTED_SYNC_PRT_SZ
#define CYREG_B1_P5_U1_DCFG0
#define CYREG_B0_P7_U1_CFG19
#define CYREG_B1_P5_U1_PLD_ORT1
#define CYREG_B0_UDB05_06_D0
#define CYREG_B0_UDB13_F1
#define CYREG_PHUB_CH4_ACTION
#define CYREG_B0_P4_U0_CFG1
#define CYREG_CAN0_RX1_AMRD
#define CYREG_B0_P5_U0_CFG19
#define CYREG_USB_ARB_RW5_WA_MSB
#define CYREG_PICU4_DISABLE_COR
#define CYREG_PRT12_SIO_CFG
#define CYREG_NVIC_SYS_HANDLER_CSR
#define CYREG_B0_P5_U0_CFG15
#define CYREG_B1_P4_U1_CFG28
#define CYREG_USB_SIE_EP6_CNT1
#define CYREG_B1_UDB04_ACTL
#define CYREG_PHUB_TDMEM105_ORIG_TD0
#define CYREG_B0_P6_U0_CFG17
#define CYREG_B1_P5_U0_CFG4
#define CYREG_B1_P2_U1_PLD_IT3
#define CYREG_PHUB_TDMEM58_ORIG_TD1
#define CYREG_B0_P3_U1_CFG22
#define CYREG_DMA_SRAM_MBASE
#define CYREG_B0_P7_U0_CFG13
#define CYREG_B1_UDB08_A0_A1
#define CYREG_CAN0_CSR_BUF_SR
#define CYREG_PHUB_CH8_ACTION
#define CYREG_B1_P4_U0_CFG26
#define CYREG_CAN0_RX15_CMD
#define CYREG_B0_P6_U1_CFG28
#define CYREG_FLSHID_MFG_CFG_CMP0_TR0
#define CYREG_B0_P5_U1_CFG24
#define CYREG_B0_UDB10_11_D1
#define CYREG_B1_P5_U1_CFG9
#define CYREG_B1_P3_U0_CFG31
#define CYREG_B1_P2_U0_CFG4
#define CYREG_PHUB_CH10_BASIC_STATUS
#define CYREG_PICU0_INTTYPE6
#define CYREG_B0_P7_U0_CFG14
#define CYREG_BCTL0_DCLK_EN1
#define CYREG_B0_P3_U1_CFG18
#define CYREG_PHUB_TDMEM35_ORIG_TD0
#define CYREG_B0_UDB05_06_CTL
#define CYREG_CAN0_RX14_ACRD
#define CYREG_B0_UDB00_CTL
#define CYREG_B0_P4_U1_PLD_ORT1
#define CYREG_B0_UDB10_ST
#define CYREG_B0_P6_U0_PLD_IT1
#define CYREG_PRT12_PS_ALIAS
#define CYREG_B0_UDB00_01_ST
#define CYREG_CAN0_TX3_CMD
#define CYREG_B0_P3_U0_CFG17
#define CYREG_FLSHID_CUST_TABLES_DAC1_M4
#define CYREG_B0_UDB03_F1
#define CYREG_B0_P0_U1_MC_CFG_CEN_CONST
#define CYREG_B0_P5_U1_PLD_IT6
#define CYREG_CAN0_RX15_ACRD
#define CYREG_PHUB_CFGMEM23_CFG0
#define CYREG_B0_P6_U1_CFG23
#define CYREG_B1_P5_U1_PLD_IT1
#define CYREG_B1_P2_U1_CFG1
#define CYREG_B0_P4_U1_CFG12
#define CYREG_B0_P7_U1_MC_CFG_XORFB
#define CYREG_PHUB_TDMEM54_ORIG_TD1
#define CYREG_FLSHID_CUST_TABLES_MINOR
#define CYREG_CAN0_TX4_CMD
#define CYREG_B1_P5_U0_MC_CFG_XORFB
#define CYREG_B0_P1_U1_CFG28
#define CYREG_B0_UDB10_11_ACTL
#define CYREG_P3BA_DATA_REG4
#define CYREG_DFB0_HOLDAH
#define CYREG_PHUB_TDMEM89_ORIG_TD0
#define CYREG_PICU0_INTSTAT
#define CYREG_B0_P3_U1_CFG3
#define CYREG_IDMUX_IRQ_CTL0
#define CYREG_B0_P5_U0_CFG14
#define CYREG_FLSHID_CUST_TABLES_IMO_92MHZ
#define CYREG_B0_P0_U1_MC_CFG_XORFB
#define CYREG_B1_UDB05_MC_00
#define CYREG_PRT3_OE_SEL0
#define CYREG_PM_STBY_CFG7
#define CYREG_B0_P4_U1_CFG28
#define CYREG_ROM_TABLE_PID3
#define CYREG_B0_P0_U1_CFG12
#define CYREG_B0_UDB00_F1
#define CYREG_CLKDIST_MSTR0
#define CYREG_PICU12_INTTYPE0
#define CYREG_B1_P4_U1_PLD_IT4
#define CYREG_PICU1_DISABLE_COR
#define CYREG_B1_P5_U1_PLD_IT7
#define CYREG_B0_P2_U0_CFG29
#define CYREG_PHUB_TDMEM83_ORIG_TD0
#define CYREG_B1_P2_U0_CFG10
#define CYREG_B1_P5_U1_CFG19
#define CYREG_B0_P4_U1_DCFG0
#define CYREG_CAN0_TX7_CMD
#define CYREG_B0_P0_U0_DCFG3
#define CYREG_PHUB_TDMEM105_ORIG_TD1
#define CYREG_P3BA_X_CURR1
#define CYREG_B0_P4_U1_CFG4
#define CYREG_B0_P4_U0_CFG0
#define CYREG_B0_P7_U0_DCFG3
#define CYREG_PHUB_TDMEM48_ORIG_TD1
#define CYREG_CLKDIST_DCFG7_CFG1
#define CYREG_B0_P6_U0_CFG26
#define CYREG_B1_UDB07_08_MSK
#define CYREG_NVIC_SYS_PRIO_HANDLER_4_7
#define CYREG_B0_UDB10_D1
#define CYREG_PICU12_SNAP
#define CYREG_USB_ARB_RW1_RA_MSB
#define CYREG_EXTMEM_DATA_MSIZE
#define CYREG_B0_UDB11_12_F0
#define CYREG_PHUB_TDMEM7_ORIG_TD0
#define CYREG_USB_ARB_RW1_RA
#define CYREG_PHUB_TDMEM24_ORIG_TD0
#define CYREG_B0_P2_U1_CFG23
#define CYREG_B0_UDB08_ST
#define CYREG_B1_P2_U1_CFG0
#define CYREG_PICU12_INTSTAT
#define CYREG_B1_UDB06_D1
#define CYREG_B0_P0_U1_CFG10
#define CYREG_B0_P4_U1_DCFG2
#define CYREG_B0_UDB04_05_MC
#define CYREG_OPAMP3_RSVD
#define CYREG_B0_P7_U1_CFG4
#define CYREG_B1_P3_U1_CFG22
#define CYREG_PICU3_INTTYPE0
#define CYREG_TMR1_CNT_CMP1
#define CYREG_B0_P0_U0_CFG11
#define CYREG_PRT0_PS_ALIAS
#define CYREG_FLSHID_CUST_TABLES_CMP1_TR1_HS
#define CYREG_B0_UDB04_05_A0
#define CYREG_B0_P1_U0_PLD_IT10
#define CYREG_B1_P3_U1_PLD_IT9
#define CYREG_B0_UDB11_MSK
#define CYREG_B0_UDB06_07_A0
#define CYREG_B0_P0_U0_CFG22
#define CYREG_BCTL1_DCLK_EN2
#define CYREG_PHUB_TDMEM5_ORIG_TD1
#define CYREG_CLKDIST_ACFG2_CFG2
#define CYREG_DFB0_CSB_SRAM_DATA_MSIZE
#define CYREG_SRAM_CODE32K_MBASE
#define CYREG_B0_UDB04_F0_F1
#define CYREG_B0_P1_U0_PLD_IT3
#define CYREG_B1_P5_U1_CFG20
#define CYREG_B1_P5_U0_CFG0
#define CYREG_B1_P4_U0_DCFG2
#define CYREG_B0_P1_U0_CFG6
#define CYREG_B0_P7_U1_MC_CFG_SET_RESET
#define CYREG_PRT0_LCD_COM_SEG
#define CYREG_B1_P4_U0_MC_CFG_CEN_CONST
#define CYREG_B1_P3_U0_CFG11
#define CYREG_B1_UDB05_06_F0
#define CYREG_USB_USBIO_CR1
#define CYREG_B0_UDB07_08_A0
#define CYREG_FLSHID_CUST_TABLES_DAC3_M1
#define CYREG_B0_P1_U1_CFG25
#define CYREG_B1_P5_U1_MC_CFG_BYPASS
#define CYREG_RESET_IPOR_CR0
#define CYREG_PRT12_DR_ALIAS
#define CYREG_PICU4_INTTYPE3
#define CYREG_PHUB_TDMEM70_ORIG_TD0
#define CYREG_B1_P3_U1_DCFG0
#define CYREG_PHUB_TDMEM2_ORIG_TD1
#define CYREG_USB_SIE_EP7_CNT1
#define CYREG_B0_P4_U1_CFG24
#define CYREG_B0_P1_U1_MC_CFG_SET_RESET
#define CYREG_CAN0_RX1_DH
#define CYREG_ROM_TABLE_ETM
#define CYREG_PHUB_TDMEM25_ORIG_TD0
#define CYREG_CAN0_RX7_ID
#define CYREG_B1_P3_U0_CFG9
#define CYREG_USB_ARB_RW4_WA
#define CYREG_B0_P4_U1_CFG3
#define CYREG_PHUB_TDMEM76_ORIG_TD0
#define CYREG_B1_P5_U1_MC_CFG_XORFB
#define CYREG_PRT4_OUT_SEL0
#define CYREG_B0_P2_U1_PLD_IT5
#define CYREG_PRT15_OUT_SEL0
#define CYREG_B0_P4_U1_MC_CFG_BYPASS
#define CYREG_USB_ARB_EP8_INT_EN
#define CYREG_B0_P1_U1_CFG16
#define CYREG_DFB0_DPB_SRAM_DATA_MBASE
#define CYREG_B0_P2_U1_CFG13
#define CYREG_DFB0_STAGEBM
#define CYREG_ITM_TRACE_PRIVILEGE
#define CYREG_B1_UDB11_12_F0
#define CYREG_CAN0_RX15_AMR
#define CYREG_USB_ARB_RW8_DR
#define CYREG_B0_P2_U1_CFG22
#define CYREG_B0_P5_U0_PLD_IT10
#define CYREG_PHUB_CFGMEM20_CFG0
#define CYREG_B1_UDB09_D0
#define CYREG_PICU15_INTTYPE4
#define CYREG_FLSHID_CUST_TABLES_WAFER_NUM
#define CYREG_B0_P0_U1_CFG7
#define CYREG_NVIC_DEBUG_FAULT_STATUS
#define CYREG_B1_P5_U1_DCFG7
#define CYREG_PHUB_TDMEM65_ORIG_TD1
#define CYREG_B1_UDB08_D0
#define CYREG_B0_P5_U1_PLD_ORT0
#define CYREG_B1_UDB04_MSK_ACTL
#define CYREG_B0_P6_U0_CFG27
#define CYREG_NPUMP_OPAMP_TR0
#define CYREG_PM_STBY_CFG5
#define CYREG_B1_P4_U0_PLD_IT5
#define CYREG_B1_P4_U1_CFG21
#define CYREG_PICU1_INTTYPE1
#define CYREG_PWRSYS_WAKE_TR1
#define CYREG_B1_UDB06_07_MSK
#define CYREG_DWT_FUNCTION_2
#define CYREG_B0_P4_U0_CFG26
#define CYREG_PANTHER_WAITPIPE
#define CYREG_CAN0_RX7_AMR
#define CYREG_B0_P4_U0_CFG29
#define CYREG_PICU4_INTTYPE1
#define CYREG_B0_P2_U1_PLD_IT10
#define CYREG_B1_P5_U0_CFG5
#define CYREG_B1_P5_U1_PLD_ORT0
#define CYREG_B0_P0_U1_CFG8
#define CYREG_B1_P2_U0_DCFG5
#define CYREG_B0_P2_U0_CFG23
#define CYREG_B0_P0_U1_DCFG7
#define CYREG_USB_SIE_EP_INT_EN
#define CYREG_CAN0_RX0_AMRD
#define CYREG_PHUB_TDMEM13_ORIG_TD0
#define CYREG_DEC_OUTSAMP
#define CYREG_SLOWCLK_X32_CR
#define CYREG_PICU0_INTTYPE4
#define CYREG_B1_P2_U1_CFG21
#define CYREG_PICU2_INTTYPE7
#define CYREG_B0_P7_U1_CFG3
#define CYREG_B0_P0_U0_DCFG5
#define CYREG_B0_UDB04_MC
#define CYREG_B1_UDB11_A1
#define CYREG_B0_P3_U0_CFG26
#define CYREG_B1_P3_U0_MC_CFG_BYPASS
#define CYREG_PHUB_CH14_ACTION
#define CYREG_PICU2_INTTYPE0
#define CYREG_USB_SIE_EP8_CNT1
#define CYREG_B1_P3_U0_MC_CFG_XORFB
#define CYREG_B0_P2_U0_DCFG7
#define CYREG_B0_P6_U1_CFG30
#define CYREG_TPIU_ITETMDATA
#define CYREG_B0_P6_U0_MC_CFG_SET_RESET
#define CYREG_B1_P3_U0_DCFG1
#define CYREG_PRT5_LCD_EN
#define CYREG_B1_UDB09_A1
#define CYREG_B1_P4_U0_CFG16
#define CYREG_CAN0_RX6_DL
#define CYREG_B0_P2_U1_DCFG4
#define CYREG_B1_UDB05_F1
#define CYREG_PRT5_LCD_COM_SEG
#define CYREG_B1_P4_U1_CFG16
#define CYREG_B0_P6_U0_CFG22
#define CYREG_B0_P4_U1_PLD_IT10
#define CYREG_B0_UDB00_A1
#define CYREG_B0_P2_U0_PLD_IT11
#define CYREG_B1_P5_U1_DCFG3
#define CYREG_ETM_CLM_TAG_SET
#define CYREG_B0_P6_U1_PLD_ORT3
#define CYREG_B0_UDB15_ACTL
#define CYREG_CLKDIST_MSTR1
#define CYREG_B1_P5_U1_CFG11
#define CYREG_FLSHID_CUST_TABLES_LOT_MSB
#define CYREG_ROM_TABLE_ITM
#define CYREG_B1_P5_U0_DCFG1
#define CYREG_B1_P3_U0_PLD_IT3
#define CYREG_B0_P1_U0_PLD_IT8
#define CYREG_PICU15_INTTYPE7
#define CYREG_B0_P4_U0_CFG3
#define CYREG_PHUB_TDMEM124_ORIG_TD1
#define CYREG_B0_P2_U0_CFG26
#define CYREG_PICU5_INTTYPE1
#define CYREG_PHUB_CFGMEM12_CFG0
#define CYREG_B0_P2_U1_CFG0
#define CYREG_B0_P0_U0_CFG28
#define CYREG_B0_P7_U1_CFG10
#define CYREG_PRT6_OUT_SEL0
#define CYREG_DFB0_ACU_SRAM_DATA_MSIZE
#define CYREG_B0_P3_U0_CFG25
#define CYREG_B0_P5_U1_CFG4
#define CYREG_B1_P3_U0_CFG2
#define CYREG_PHUB_TDMEM66_ORIG_TD0
#define CYREG_B0_P7_U1_CFG27
#define CYREG_P3BA_DATCFG1
#define CYREG_B0_P7_U0_CFG23
#define CYREG_USB_ARB_RW7_RA
#define CYREG_B0_P4_U0_CFG2
#define CYREG_B0_UDB06_07_D0
#define CYREG_B0_UDB14_15_D1
#define CYREG_B0_UDB04_D0
#define CYREG_B1_P4_U1_PLD_IT8
#define CYREG_PHUB_TDMEM93_ORIG_TD1
#define CYREG_B1_P4_U1_CFG13
#define CYREG_PHUB_CH15_ACTION
#define CYREG_USB_ARB_RW1_WA_MSB
#define CYREG_B0_P5_U0_CFG17
#define CYREG_B0_UDB12_CTL
#define CYREG_PHUB_TDMEM113_ORIG_TD0
#define CYREG_B0_P6_U0_CFG25
#define CYREG_B0_P0_U1_CFG25
#define CYREG_B1_P3_U1_CFG31
#define CYREG_B0_UDB10_11_A0
#define CYREG_SRAM_DATA_MSIZE
#define CYREG_B0_P4_U0_PLD_IT6
#define CYREG_B0_UDB04_F1
#define CYREG_B0_P7_U0_CFG6
#define CYREG_B0_UDB15_A0_A1
#define CYREG_B0_P4_U1_CFG11
#define CYREG_PRT0_OUT_SEL0
#define CYREG_B1_P2_U1_CFG29
#define CYREG_B0_P4_U1_DCFG3
#define CYREG_B0_P4_U1_MC_CFG_CEN_CONST
#define CYREG_USB_ARB_RW2_WA_MSB
#define CYREG_B0_P3_U1_PLD_IT5
#define CYREG_B0_UDB12_D0_D1
#define CYREG_B0_UDB09_10_MC
#define CYREG_B0_P4_U0_CFG23
#define CYREG_B1_P2_U1_CFG19
#define CYREG_B0_P6_U1_CFG26
#define CYREG_B0_UDB01_A1
#define CYREG_USB_ARB_EP2_CFG
#define CYREG_DMA_SRAM16K_MSIZE
#define CYREG_B0_P0_U0_PLD_ORT2
#define CYREG_B0_P5_U1_CFG15
#define CYREG_PHUB_TDMEM125_ORIG_TD0
#define CYREG_B0_P3_U0_CFG23
#define CYREG_PICU15_INTTYPE2
#define CYREG_B1_P5_U0_CFG22
#define CYREG_B1_P3_U0_DCFG6
#define CYREG_B0_P4_U0_CFG21
#define CYREG_PM_STBY_CFG12
#define CYREG_B0_P4_U1_PLD_IT4
#define CYREG_B0_UDB13_14_A1
#define CYREG_B0_P5_U0_DCFG0
#define CYREG_B0_UDB14_ACTL
#define CYREG_PICU2_DISABLE_COR
#define CYREG_CLKDIST_DCFG1_CFG1
#define CYREG_B0_P3_U0_PLD_ORT0
#define CYREG_B1_UDB06_MSK_ACTL
#define CYREG_B1_P2_U0_MC_CFG_XORFB
#define CYREG_B1_P4_U0_CFG9
#define CYREG_DAC2_STROBE
#define CYREG_B0_P3_U0_CFG9
#define CYREG_B1_P5_U0_CFG17
#define CYREG_PRT3_OE_SEL1
#define CYREG_B0_UDB09_10_ST
#define CYREG_USB_ARB_RW5_RA
#define CYREG_NVIC_PRI_11
#define CYREG_B1_P3_U0_DCFG5
#define CYREG_B0_P6_U0_PLD_ORT3
#define CYREG_B0_P5_U1_DCFG3
#define CYREG_B0_P5_U1_PLD_IT9
#define CYREG_PHUB_TDMEM4_ORIG_TD0
#define CYREG_PHUB_TDMEM127_ORIG_TD1
#define CYREG_B0_UDB11_D0_D1
#define CYREG_B0_P3_U1_PLD_IT0
#define CYREG_B1_P2_U1_CFG22
#define CYREG_B1_P3_U0_CFG25
#define CYREG_B1_UDB04_05_D1
#define CYREG_PHUB_TDMEM38_ORIG_TD0
#define CYREG_NVIC_PRI_12
#define CYREG_B0_P1_U0_PLD_ORT3
#define CYREG_PHUB_CH11_ACTION
#define CYREG_CAN0_RX4_ID
#define CYREG_B0_P1_U0_CFG19
#define CYREG_B0_UDB12_A0_A1
#define CYREG_B0_P1_U1_PLD_ORT3
#define CYREG_PHUB_TDMEM68_ORIG_TD0
#define CYREG_PANTHER_DEVICE_ID
#define CYREG_SPC_DMA_DATA
#define CYREG_P3BA_MSTR_HRDATA1
#define CYREG_PICU0_INTTYPE1
#define CYREG_PHUB_TDMEM45_ORIG_TD1
#define CYREG_B0_UDB00_ST_CTL
#define CYREG_ROM_TABLE_CID3
#define CYREG_B0_P5_U0_MC_CFG_SET_RESET
#define CYREG_B0_UDB11_MC
#define CYREG_B1_P2_U0_CFG21
#define CYREG_B1_UDB11_MC_00
#define CYREG_B0_P4_U0_MC_CFG_BYPASS
#define CYREG_B1_UDB09_D0_D1
#define CYREG_USB_ARB_EP8_CFG
#define CYREG_B1_UDB06_A0_A1
#define CYREG_DAC3_STROBE
#define CYREG_CAN0_RX3_AMR
#define CYREG_PHUB_TDMEM5_ORIG_TD0
#define CYREG_PICU12_INTTYPE1
#define CYREG_B0_P6_U0_DCFG7
#define CYREG_B1_P3_U0_CFG16
#define CYREG_B1_P4_U1_CFG9
#define CYREG_PM_STBY_CFG6
#define CYREG_PHUB_CH11_BASIC_STATUS
#define CYREG_B0_P6_U1_CFG14
#define CYREG_CLKDIST_DCFG4_CFG1
#define CYREG_B0_P6_U1_CFG10
#define CYREG_USB_ARB_EP1_INT_EN
#define CYREG_B1_UDB07_08_D0
#define CYREG_PICU4_INTTYPE7
#define CYREG_B0_UDB11_MSK_ACTL
#define CYREG_B0_P1_U0_PLD_IT0
#define CYREG_NVIC_PRI_14
#define CYREG_B0_UDB00_01_MSK
#define CYREG_B1_UDB11_D0_D1
#define CYREG_B0_UDB15_F1
#define CYREG_PHUB_CFGMEM8_CFG1
#define CYREG_B0_P2_U0_CFG13
#define CYREG_B0_P7_U0_PLD_IT11
#define CYREG_B1_UDB09_A0_A1
#define CYREG_B1_UDB04_05_A1
#define CYREG_P3BA_OFFSETADDR1
#define CYREG_PHUB_TDMEM52_ORIG_TD0
#define CYREG_B0_P3_U1_DCFG6
#define CYREG_B1_P4_U0_PLD_ORT3
#define CYREG_IDMUX_DRQ_CTL5
#define CYREG_PHUB_CH5_BASIC_STATUS
#define CYREG_B0_P6_U1_DCFG6
#define CYREG_CLKDIST_UCFG
#define CYREG_B0_P6_U1_CFG13
#define CYREG_PICU5_INTTYPE7
#define CYREG_PRT15_DR_15_ALIAS
#define CYREG_B0_P6_U0_PLD_IT0
#define CYREG_B1_P5_U0_CFG23
#define CYREG_B0_P2_U1_PLD_IT2
#define CYREG_B0_UDB07_MSK
#define CYREG_B1_P3_U1_PLD_ORT3
#define CYREG_PHUB_CFGMEM18_CFG0
#define CYREG_B0_P6_U0_CFG1
#define CYREG_B0_P1_U1_MC_CFG_XORFB
#define CYREG_B0_P3_U1_PLD_ORT1
#define CYREG_DFB0_HOLDBS
#define CYREG_B0_UDB12_13_F1
#define CYREG_PHUB_TDMEM120_ORIG_TD0
#define CYREG_B0_UDB07_08_CTL
#define CYREG_CAN0_TX1_DH
#define CYREG_B0_UDB11_12_ST
#define CYREG_B0_P4_U0_MC_CFG_CEN_CONST
#define CYREG_B1_P2_U0_PLD_IT11
#define CYREG_P3BA_SEQCFG2
#define CYREG_B0_P2_U0_CFG20
#define CYREG_PHUB_TDMEM120_ORIG_TD1
#define CYREG_FLSHID_MFG_CFG_CMP2_TR0
#define CYREG_B1_P2_U0_CFG23
#define CYREG_ROM_TABLE_PID5
#define CYREG_B1_P2_U1_CFG6
#define CYREG_PICU5_INTSTAT
#define CYREG_PM_AVAIL_SR2
#define CYREG_B1_P4_U1_CFG2
#define CYREG_B0_P2_U1_PLD_IT4
#define CYREG_PHUB_TDMEM11_ORIG_TD0
#define CYREG_B0_P7_U1_CFG29
#define CYREG_B0_UDB03_F0_F1
#define CYREG_PHUB_CH9_BASIC_CFG
#define CYREG_B1_P3_U0_CFG4
#define CYREG_ETM_TRACE_ENB_EVENT
#define CYREG_FLSHID_CUST_TABLES_IMO_USB
#define CYREG_B0_UDB01_02_MSK
#define CYREG_B1_P4_U1_CFG8
#define CYREG_B0_UDB00_A0_A1
#define CYREG_B0_UDB02_03_D0
#define CYREG_B0_UDB01_ST_CTL
#define CYREG_B1_UDB06_07_A0
#define CYREG_B0_P5_U1_DCFG7
#define CYREG_B0_P3_U0_PLD_IT9
#define CYREG_ETM_SYNC_FREQ
#define CYREG_PRT1_LCD_EN
#define CYREG_B0_UDB05_06_A1
#define CYREG_CAN0_RX3_AMRD
#define CYREG_B0_P1_U1_CFG13
#define CYREG_FLSHID_CUST_TABLES_DAC2_M5
#define CYREG_USB_ARB_RW6_WA
#define CYREG_PRT15_PS15_ALIAS
#define CYREG_B1_UDB07_F0_F1
#define CYREG_FPB_FP_COMP_0
#define CYREG_NVIC_SETENA0
#define CYREG_CAN0_RX9_ACRD
#define CYREG_B0_P3_U1_PLD_IT8
#define CYREG_B0_P2_U0_CFG8
#define CYREG_B0_UDB02_CTL
#define CYREG_CLKDIST_ACFG1_CFG3
#define CYREG_B0_UDB12_D0
#define CYREG_PRT3_DR_ALIAS
#define CYREG_PM_STBY_CFG3
#define CYREG_B1_P2_U0_CFG20
#define CYREG_B0_P5_U1_CFG22
#define CYREG_B0_P4_U1_CFG30
#define CYREG_PRT0_OUT_SEL1
#define CYREG_PHUB_TDMEM36_ORIG_TD0
#define CYREG_B1_P2_U1_CFG31
#define CYREG_B0_P5_U0_DCFG5
#define CYREG_EMIF_MEM_DWN
#define CYREG_B0_P3_U1_CFG7
#define CYREG_BCTL1_WAIT_CFG
#define CYREG_B1_P5_U0_CFG28
#define CYREG_B0_UDB02_F0
#define CYREG_IO_PC_PRT15_PC4
#define CYREG_B0_P2_U0_CFG22
#define CYREG_PHUB_TDMEM81_ORIG_TD1
#define CYREG_B0_P0_U1_CFG23
#define CYREG_DWT_LSU_COUNT
#define CYREG_B0_P7_U0_CFG19
#define CYREG_PHUB_TDMEM87_ORIG_TD0
#define CYREG_PHUB_TDMEM29_ORIG_TD1
#define CYREG_B1_UDB07_D0_D1
#define CYREG_ANAIF_CFG_MISC_CR0
#define CYREG_CAN0_TX0_DL
#define CYREG_B1_P3_U1_CFG28
#define CYREG_B0_P5_U0_CFG30
#define CYREG_B1_P5_U0_DCFG3
#define CYREG_PM_ACT_CFG8
#define CYREG_B0_P7_U0_PLD_ORT3
#define CYREG_B0_P5_U0_MC_CFG_BYPASS
#define CYREG_PHUB_TDMEM84_ORIG_TD1
#define CYREG_B0_P7_U0_PLD_IT2
#define CYREG_B1_UDB05_06_MSK
#define CYREG_B0_P7_U1_CFG1
#define CYREG_MLOGIC_REV_ID
#define CYREG_B1_P2_U1_CFG12
#define CYREG_PRT0_OE_SEL0
#define CYREG_B0_UDB12_13_F0
#define CYREG_B0_UDB08_09_D0
#define CYREG_B0_P5_U1_DCFG2
#define CYREG_B1_P5_U0_CFG20
#define CYREG_PHUB_TDMEM67_ORIG_TD1
#define CYREG_B0_P6_U0_PLD_IT11
#define CYREG_B0_P1_U0_CFG2
#define CYREG_B0_P6_U0_CFG16
#define CYREG_B0_P7_U1_MC_CFG_BYPASS
#define CYREG_B0_P3_U1_CFG21
#define CYREG_B0_UDB11_ST
#define CYREG_B1_P3_U1_CFG12
#define CYREG_B1_P5_U0_PLD_IT5
#define CYREG_B0_P0_U1_CFG21
#define CYREG_B1_UDB04_ST
#define CYREG_FPB_FP_COMP_7
#define CYREG_CAN0_TX2_DL
#define CYREG_B0_UDB12_D1
#define CYREG_B0_P7_U1_CFG17
#define CYREG_B0_P2_U1_CFG9
#define CYREG_B0_UDB09_MC
#define CYREG_B0_P1_U0_CFG9
#define CYREG_B1_P2_U1_CFG18
#define CYREG_B0_UDB00_MC_00
#define CYREG_B0_P1_U0_CFG21
#define CYREG_B1_UDB08_F1
#define CYREG_PHUB_TDMEM72_ORIG_TD0
#define CYREG_B0_P3_U0_CFG30
#define CYREG_B0_P1_U1_CFG0
#define CYREG_CAN0_RX1_ID
#define CYREG_B0_P1_U0_CFG7
#define CYREG_B0_P5_U0_CFG27
#define CYREG_PRT6_DR_ALIAS
#define CYREG_B1_UDB08_F0
#define CYREG_B0_P2_U1_MC_CFG_XORFB
#define CYREG_B1_UDB08_MC
#define CYREG_B0_P6_U0_CFG19
#define CYREG_B1_P5_U1_CFG18
#define CYREG_B0_P1_U0_MC_CFG_CEN_CONST
#define CYREG_USB_SIE_EP1_CR0
#define CYREG_USB_ARB_EP1_CFG
#define CYREG_B0_UDB13_A0_A1
#define CYREG_B0_UDB07_08_D0
#define CYREG_CAN0_CSR_CMD
#define CYREG_B1_UDB09_10_D0
#define CYREG_PHUB_TDMEM16_ORIG_TD0
#define CYREG_B0_P7_U0_CFG0
#define CYREG_B0_UDB14_A0_A1
#define CYREG_B0_P7_U1_PLD_IT4
#define CYREG_PHUB_TDMEM44_ORIG_TD1
#define CYREG_FLSHID_MFG_CFG_IMO_TR1
#define CYREG_B0_P6_U1_CFG20
#define CYREG_PRT2_OE_SEL1
#define CYREG_B1_P2_U0_MC_CFG_CEN_CONST
#define CYREG_B1_P5_U0_DCFG0
#define CYREG_PHUB_TDMEM86_ORIG_TD1
#define CYREG_B0_P2_U1_CFG15
#define CYREG_B0_UDB10_MSK_ACTL
#define CYREG_ROM_TABLE_FPB
#define CYREG_B0_P2_U0_CFG0
#define CYREG_B0_UDB06_MSK_ACTL
#define CYREG_B1_UDB09_10_D1
#define CYREG_PHUB_TDMEM114_ORIG_TD0
#define CYREG_B0_P0_U0_PLD_IT11
#define CYREG_B1_P4_U1_DCFG0
#define CYREG_ROM_TABLE_MEMTYPE
#define CYREG_B1_P2_U0_PLD_IT3
#define CYREG_B0_P1_U1_DCFG7
#define CYREG_B0_UDB14_MC_00
#define CYREG_B0_P6_U0_CFG11
#define CYREG_B0_P4_U1_CFG25
#define CYREG_B0_P1_U1_PLD_IT8
#define CYREG_B0_P4_U1_CFG29
#define CYREG_B1_P2_U0_CFG8
#define CYREG_B0_P1_U1_PLD_IT1
#define CYREG_PICU12_INTTYPE3
#define CYREG_FLSHID_CUST_TABLES_DAC0_M8
#define CYREG_CAN0_RX13_ACRD
#define CYREG_B0_P2_U0_PLD_IT8
#define CYREG_B1_UDB10_11_MC
#define CYREG_PWRSYS_BG_TR
#define CYREG_B0_UDB07_CTL
#define CYREG_B0_UDB15_D0_D1
#define CYREG_B1_P4_U1_CFG22
#define CYREG_B1_P5_U1_CFG2
#define CYREG_FLSHID_MFG_CFG_CMP1_TR1
#define CYREG_B0_P0_U0_CFG8
#define CYREG_B1_P5_U1_CFG28
#define CYREG_USB_ARB_RW2_RA_MSB
#define CYREG_B1_P4_U1_DCFG3
#define CYREG_B0_UDB08_A1
#define CYREG_B1_P3_U1_PLD_IT11
#define CYREG_B0_P3_U0_CFG11
#define CYREG_CAN0_CSR_INT_SR
#define CYREG_B0_P0_U1_MC_CFG_BYPASS
#define CYREG_B0_P1_U1_PLD_IT7
#define CYREG_B0_P1_U1_CFG2
#define CYREG_B1_P2_U0_CFG16
#define CYREG_B1_P2_U0_PLD_ORT3
#define CYREG_B0_UDB05_D0
#define CYREG_B0_P1_U0_PLD_IT1
#define CYREG_PHUB_CFGMEM2_CFG0
#define CYREG_PHUB_TDMEM27_ORIG_TD0
#define CYREG_B0_UDB02_D0
#define CYREG_PHUB_CFGMEM11_CFG1
#define CYREG_B1_UDB05_F0
#define CYREG_B0_P3_U0_CFG14
#define CYREG_B1_P5_U1_CFG30
#define CYREG_B1_UDB09_10_MC
#define CYREG_B0_P2_U1_CFG30
#define CYREG_B1_P4_U1_CFG19
#define CYREG_B0_P3_U1_CFG27
#define CYREG_PHUB_TDMEM34_ORIG_TD0
#define CYREG_B0_P2_U0_CFG21
#define CYREG_USB_EP0_DR4
#define CYREG_PHUB_TDMEM75_ORIG_TD1
#define CYREG_B0_UDB14_15_ACTL
#define CYREG_B1_UDB05_06_A0
#define CYREG_CAN0_RX9_ID
#define CYREG_B0_P2_U1_MC_CFG_SET_RESET
#define CYREG_B0_UDB06_A1
#define CYREG_B0_P7_U1_PLD_IT8
#define CYREG_BCTL0_MBCLK_EN
#define CYREG_B1_P2_U1_PLD_ORT1
#define CYREG_B0_P0_U0_CFG24
#define CYREG_B0_P4_U1_DCFG7
#define CYREG_B0_P2_U1_PLD_IT6
#define CYREG_B0_P0_U1_CFG29
#define CYREG_USB_ARB_EP7_CFG
#define CYREG_B0_P6_U1_PLD_IT6
#define CYREG_CAN0_CSR_INT_EN
#define CYREG_B0_P2_U1_CFG16
#define CYREG_FLSHID_CUST_TABLES_CMP0_TR0_HS
#define CYREG_B1_P2_U0_PLD_ORT0
#define CYREG_PHUB_CH5_ACTION
#define CYREG_ROM_TABLE_PID0
#define CYREG_B0_P2_U0_PLD_IT2
#define CYREG_PHUB_CH18_BASIC_STATUS
#define CYREG_PICU0_INTTYPE7
#define CYREG_USB_SIE_EP6_CR0
#define CYREG_B0_P4_U0_CFG14
#define CYREG_IO_PC_PRT15_PC5
#define CYREG_B1_P2_U0_CFG24
#define CYREG_PHUB_TDMEM13_ORIG_TD1
#define CYREG_SLOWCLK_ILO_CR0
#define CYREG_B0_P4_U0_PLD_IT10
#define CYREG_PHUB_CFGMEM21_CFG1
#define CYREG_B0_UDB02_03_F0
#define CYREG_B1_UDB08_09_CTL
#define CYREG_PM_STBY_CFG4
#define CYREG_B1_P5_U0_CFG29
#define CYREG_B1_UDB10_A1
#define CYREG_B0_P5_U1_CFG23
#define CYREG_B0_UDB10_A1
#define CYREG_B0_UDB01_ST
#define CYREG_CAN0_CSR_CFG
#define CYREG_B1_P2_U1_CFG20
#define CYREG_B0_P0_U1_CFG24
#define CYREG_B0_P3_U0_MC_CFG_BYPASS
#define CYREG_B0_P6_U1_PLD_IT2
#define CYREG_BCTL1_BCLK_EN2
#define CYREG_PHUB_TDMEM20_ORIG_TD0
#define CYREG_B1_P3_U1_DCFG5
#define CYREG_B0_P0_U1_DCFG2
#define CYREG_B1_P4_U0_CFG20
#define CYREG_PHUB_CH15_BASIC_STATUS
#define CYREG_B0_P6_U1_PLD_IT0
#define CYREG_PHUB_TDMEM59_ORIG_TD1
#define CYREG_B0_UDB03_04_MC
#define CYREG_B1_P5_U0_PLD_ORT3
#define CYREG_PHUB_TDMEM38_ORIG_TD1
#define CYREG_PM_STBY_CFG8
#define CYREG_PHUB_CH6_BASIC_STATUS
#define CYREG_B0_P2_U0_CFG30
#define CYREG_B1_P5_U0_DCFG4
#define CYREG_B0_P1_U0_MC_CFG_BYPASS
#define CYREG_CAN0_RX9_DH
#define CYREG_B0_UDB10_11_A1
#define CYREG_B1_P5_U1_PLD_IT9
#define CYREG_B1_P4_U0_CFG30
#define CYREG_B0_UDB01_F1
#define CYREG_B0_P6_U1_CFG11
#define CYREG_B0_P7_U0_DCFG0
#define CYREG_B0_P2_U1_CFG12
#define CYREG_B1_UDB04_05_F0
#define CYREG_P3BA_DATA_REG1
#define CYREG_PRT6_LCD_EN
#define CYREG_B0_P4_U1_MC_CFG_XORFB
#define CYREG_PHUB_TDMEM48_ORIG_TD0
#define CYREG_PRT4_INP_DIS
#define CYREG_PHUB_TDMEM65_ORIG_TD0
#define CYREG_FLSHID_CUST_TABLES_DEC_M8
#define CYREG_B0_P0_U1_DCFG3
#define CYREG_B0_P6_U0_CFG14
#define CYREG_PICU2_INTTYPE5
#define CYREG_B0_P3_U1_CFG31
#define CYREG_B0_P5_U0_CFG4
#define CYREG_B0_P7_U1_CFG11
#define CYREG_PRT12_OUT_SEL0
#define CYREG_PRT15_OE_SEL1
#define CYREG_B1_P5_U1_PLD_IT8
#define CYREG_NVIC_CLRPEND0
#define CYREG_PHUB_TDMEM32_ORIG_TD0
#define CYREG_B0_P0_U0_CFG17
#define CYREG_PHUB_CH12_BASIC_CFG
#define CYREG_B1_UDB06_MSK
#define CYREG_PHUB_CH22_BASIC_STATUS
#define CYREG_B0_P0_U0_PLD_IT0
#define CYREG_NVIC_PRI_27
#define CYREG_B0_UDB13_14_A0
#define CYREG_CAN0_RX0_DH
#define CYREG_CAN0_TX5_DL
#define CYREG_B0_P1_U1_CFG6
#define CYREG_B1_P4_U1_DCFG4
#define CYREG_B0_UDB08_D0_D1
#define CYREG_B0_UDB00_MSK_ACTL
#define CYREG_B0_UDB13_A0
#define CYREG_B0_P0_U0_CFG9
#define CYREG_PM_AVAIL_CR2
#define CYREG_CLKDIST_ACFG3_CFG2
#define CYREG_PHUB_CH15_BASIC_CFG
#define CYREG_DWT_EXC_OVHD_COUNT
#define CYREG_B0_P6_U0_MC_CFG_XORFB
#define CYREG_B1_P4_U1_PLD_ORT3
#define CYREG_B0_UDB03_04_A0
#define CYREG_B1_P2_U1_DCFG5
#define CYREG_B0_P4_U0_PLD_ORT1
#define CYREG_FLSHID_CUST_TABLES_CMP2_TR0_HS
#define CYREG_FLSHID_CUST_TABLES_DEC_M3
#define CYREG_PRT3_INP_DIS
#define CYREG_PRT3_LCD_COM_SEG
#define CYREG_B1_P4_U1_PLD_IT0
#define CYREG_B1_P3_U0_PLD_IT7
#define CYREG_B0_P7_U0_CFG5
#define CYREG_B0_P1_U1_DCFG1
#define CYREG_B0_P4_U0_PLD_IT7
#define CYREG_B0_P7_U0_CFG3
#define CYREG_B1_UDB10_D0
#define CYREG_CAN0_RX12_AMR
#define CYREG_USB_ARB_RW3_WA
#define CYREG_B0_P5_U1_CFG25
#define CYREG_USB_SIE_EP5_CR0
#define CYREG_PRT0_DR_ALIAS
#define CYREG_B1_UDB11_MSK_ACTL
#define CYREG_FLSHID_MFG_CFG_CMP3_TR1
#define CYREG_PWRSYS_SLP_TR
#define CYREG_PRT2_OUT_SEL1
#define CYREG_B0_UDB08_D0
#define CYREG_B0_UDB00_01_ACTL
#define CYREG_B0_P4_U1_CFG1
#define CYREG_CLKDIST_AMASK
#define CYREG_B0_P0_U0_PLD_ORT0
#define CYREG_B0_UDB03_D1
#define CYREG_PICU1_INTTYPE3
#define CYREG_B1_P5_U0_PLD_IT6
#define CYREG_CAN0_TX4_DH
#define CYREG_I2C_TMOUT_CSR
#define CYREG_B0_P2_U1_MC_CFG_BYPASS
#define CYREG_B0_P2_U0_CFG3
#define CYREG_DFB0_DSI_CTRL
#define CYREG_B0_P6_U1_PLD_IT8
#define CYREG_B0_P1_U1_DCFG3
#define CYREG_B1_UDB06_MC
#define CYREG_PICU4_INTTYPE0
#define CYREG_PHUB_TDMEM96_ORIG_TD0
#define CYREG_PRT15_SYNC_OUT
#define CYREG_CLKDIST_DCFG3_CFG0
#define CYREG_FLSHID_CUST_TABLES_DAC3_M4
#define CYREG_PHUB_CFGMEM0_CFG1
#define CYREG_PHUB_TDMEM102_ORIG_TD1
#define CYREG_B0_UDB06_MC
#define CYREG_B0_P1_U1_DCFG4
#define CYREG_PHUB_TDMEM46_ORIG_TD0
#define CYREG_PRT5_INP_DIS
#define CYREG_FLSHID_CUST_TABLES_Y_LOC
#define CYREG_B1_P2_U1_CFG23
#define CYREG_B1_P4_U1_CFG27
#define CYREG_PM_ACT_CFG5
#define CYREG_B1_P3_U1_DCFG6
#define CYREG_B0_P3_U1_MC_CFG_XORFB
#define CYREG_B1_P3_U1_CFG10
#define CYREG_B0_P7_U1_DCFG0
#define CYREG_CAN0_RX4_ACRD
#define CYREG_B0_UDB06_07_D1
#define CYREG_B0_P2_U0_CFG2
#define CYREG_PHUB_TDMEM71_ORIG_TD0
#define CYREG_B0_UDB15_F0
#define CYREG_B0_P1_U0_CFG30
#define CYREG_B1_P3_U1_PLD_IT10
#define CYREG_B0_UDB13_MC_00
#define CYREG_B0_UDB07_MSK_ACTL
#define CYREG_B0_P0_U0_CFG0
#define CYREG_BCTL1_BCLK_EN3
#define CYREG_B1_P3_U1_PLD_ORT2
#define CYREG_B0_P5_U1_DCFG6
#define CYREG_B0_P0_U0_PLD_ORT3
#define CYREG_B0_P6_U1_CFG1
#define CYREG_B0_P2_U0_PLD_IT4
#define CYREG_PHUB_CH23_BASIC_CFG
#define CYREG_B0_UDB13_ST
#define CYREG_B1_P5_U0_CFG16
#define CYREG_CAN0_RX13_DH
#define CYREG_PICU5_INTTYPE4
#define CYREG_PHUB_CFGMEM9_CFG0
#define CYREG_USB_ARB_RW2_DR
#define CYREG_PM_ACT_CFG4
#define CYREG_PHUB_TDMEM53_ORIG_TD1
#define CYREG_B1_P2_U1_PLD_IT11
#define CYREG_B0_P4_U0_CFG10
#define CYREG_SFR_GPIO12_SEL
#define CYREG_B1_P4_U1_CFG3
#define CYREG_B0_P5_U0_DCFG6
#define CYREG_B0_UDB13_14_ST
#define CYREG_IDMUX_IRQ_CTL5
#define CYREG_CAN0_RX8_ID
#define CYREG_B1_UDB10_D1
#define CYREG_B1_UDB09_10_A0
#define CYREG_PM_AVAIL_SR4
#define CYREG_B1_P3_U1_CFG13
#define CYREG_B0_P2_U1_CFG17
#define CYREG_B0_UDB13_D0
#define CYREG_B0_UDB01_A0_A1
#define CYREG_B1_P5_U0_CFG24
#define CYREG_ROM_TABLE_PID1
#define CYREG_RESET_IPOR_CR2
#define CYREG_B0_P2_U0_CFG24
#define CYREG_PM_ACT_CFG11
#define CYREG_B1_P3_U1_CFG16
#define CYREG_B0_P2_U1_CFG14
#define CYREG_B1_P3_U1_MC_CFG_XORFB
#define CYREG_CLKDIST_ACFG0_CFG1
#define CYREG_PHUB_CFGMEM4_CFG0
#define CYREG_B0_UDB03_MSK_ACTL
#define CYREG_CAN0_TX1_CMD
#define CYREG_B1_P2_U0_PLD_IT7
#define CYREG_FLSHID_CUST_TABLES_DAC3_M6
#define CYREG_PHUB_TDMEM58_ORIG_TD0
#define CYREG_B1_P2_U1_CFG30
#define CYREG_BCTL1_BCLK_EN0
#define CYREG_FPB_FP_COMP_5
#define CYREG_B0_P2_U1_DCFG0
#define CYREG_DWT_CPI_COUNT
#define CYREG_B1_UDB06_F0_F1
#define CYREG_B0_UDB09_F0_F1
#define CYREG_PRT2_CAPS_SEL
#define CYREG_B1_P3_U0_CFG20
#define CYREG_CAN0_RX2_AMRD
#define CYREG_B0_P1_U1_PLD_IT5
#define CYREG_B0_P0_U1_PLD_ORT0
#define CYREG_DMA_SRAM64K_MBASE
#define CYREG_B0_UDB08_MSK
#define CYREG_PHUB_CH19_BASIC_STATUS
#define CYREG_TPIU_ITATBCTR0
#define CYREG_B1_P2_U0_DCFG1
#define CYREG_IO_PC_PRT15_7_6_PC1
#define CYREG_B0_P5_U0_CFG26
#define CYREG_B0_P0_U1_CFG5
#define CYREG_B0_P4_U0_DCFG5
#define CYREG_B0_P2_U0_CFG10
#define CYREG_CLKDIST_ACFG3_CFG3
#define CYREG_B0_UDB12_13_CTL
#define CYREG_FASTCLK_PLL_CFG0
#define CYREG_B0_P4_U0_PLD_ORT2
#define CYREG_FLSHID_MFG_CFG_CMP1_TR0
#define CYREG_PRT5_CAPS_SEL
#define CYREG_CAN0_RX7_AMRD
#define CYREG_B0_P3_U0_PLD_ORT2
#define CYREG_B1_P5_U1_CFG15
#define CYREG_B0_UDB08_09_F0
#define CYREG_B0_P0_U1_DCFG0
#define CYREG_B0_P4_U0_MC_CFG_SET_RESET
#define CYREG_IDMUX_DRQ_CTL0
#define CYREG_B0_UDB14_ST
#define CYREG_B1_P2_U0_CFG27
#define CYREG_P3BA_Y_START
#define CYREG_B1_UDB09_F0
#define CYREG_PM_STBY_CFG2
#define CYREG_BCTL1_BCLK_EN1
#define CYREG_B0_UDB06_MC_00
#define CYREG_USB_MEM_DATA_MSIZE
#define CYREG_P3BA_Y_CURR
#define CYREG_FASTCLK_XMHZ_CFG1
#define CYREG_B1_P2_U1_CFG11
#define CYREG_B0_UDB15_MC_00
#define CYREG_ETM_ITTRIGOUT
#define CYREG_B0_UDB03_A0_A1
#define CYREG_B1_P2_U1_CFG25
#define CYREG_B1_P2_U1_PLD_IT2
#define CYREG_P3BA_SEQCFG1
#define CYREG_P3BA_BIST_EN
#define CYREG_BCTL0_DCLK_EN2
#define CYREG_B1_P3_U0_MC_CFG_SET_RESET
#define CYREG_B0_P3_U0_CFG15
#define CYREG_EMIF_WP_WAIT_STATES
#define CYREG_B0_P3_U0_MC_CFG_SET_RESET
#define CYREG_B0_P0_U1_PLD_IT6
#define CYREG_NVIC_PRI_28
#define CYREG_B0_UDB08_F1
#define CYREG_B0_P3_U1_CFG30
#define CYREG_B1_P4_U0_CFG22
#define CYREG_B0_P5_U0_PLD_IT6
#define CYREG_B0_UDB13_14_MSK
#define CYREG_CAN0_RX8_DH
#define CYREG_RESET_IPOR_CR1
#define CYREG_B0_P1_U0_DCFG4
#define CYREG_B0_P5_U0_CFG1
#define CYREG_PM_WAKEUP_CFG2
#define CYREG_B1_P3_U0_PLD_IT8
#define CYREG_B1_UDB06_F0
#define CYREG_B1_P2_U0_PLD_IT9
#define CYREG_B1_P3_U0_CFG5
#define CYREG_CAN0_RX11_CMD
#define CYREG_PHUB_TDMEM43_ORIG_TD1
#define CYREG_CAN0_RX5_ID
#define CYREG_B0_P6_U1_MC_CFG_SET_RESET
#define CYREG_B1_P5_U1_PLD_IT10
#define CYREG_MLOGIC_DEBUG
#define CYREG_B0_P6_U1_PLD_IT4
#define CYREG_B0_P1_U1_CFG15
#define CYREG_B1_UDB04_A0
#define CYREG_PHUB_TDMEM9_ORIG_TD0
#define CYREG_IDMUX_DRQ_CTL1
#define CYREG_CAN0_RX10_AMR
#define CYREG_PWRSYS_HIB_TR0
#define CYREG_B0_P0_U1_CFG11
#define CYREG_CAN0_RX2_ACRD
#define CYREG_CLKDIST_DLY0
#define CYREG_PHUB_TDMEM111_ORIG_TD0
#define CYREG_B0_P1_U0_CFG24
#define CYREG_PHUB_CFGMEM1_CFG0
#define CYREG_DFB0_STAGEA
#define CYREG_SRAM_CODE_MSIZE
#define CYREG_CAN0_RX13_AMRD
#define CYREG_B0_P2_U0_PLD_IT7
#define CYREG_B1_P4_U0_CFG8
#define CYREG_B0_UDB06_CTL
#define CYREG_B0_UDB01_F0
#define CYREG_PHUB_TDMEM60_ORIG_TD1
#define CYREG_B1_UDB07_D0
#define CYREG_PHUB_CFGMEM11_CFG0
#define CYREG_BCTL0_MDCLK_EN
#define CYREG_B1_P2_U0_CFG9
#define CYREG_B0_UDB08_09_ACTL
#define CYREG_PRT1_SYNC_OUT
#define CYREG_B1_P4_U1_MC_CFG_BYPASS
#define CYREG_PICU5_INTTYPE5
#define CYREG_P3BA_CMP_RSLT3
#define CYREG_B1_UDB07_A0
#define CYREG_B0_P1_U1_CFG23
#define CYREG_B0_P6_U0_DCFG0
#define CYREG_PHUB_CH7_BASIC_STATUS
#define CYREG_B1_P3_U0_CFG13
#define CYREG_PHUB_CFGMEM5_CFG1
#define CYREG_B0_P7_U1_CFG24
#define CYREG_CAN0_RX13_DL
#define CYREG_B0_P7_U1_DCFG4
#define CYREG_B0_P0_U0_CFG7
#define CYREG_B0_P5_U0_PLD_IT0
#define CYREG_PHUB_CH3_BASIC_CFG
#define CYREG_B1_UDB06_ST
#define CYREG_SFR_GPIO1_SEL
#define CYREG_CAN0_RX11_AMRD
#define CYREG_FLSHID_CUST_TABLES_DAC0_M4
#define CYREG_PHUB_CFGMEM10_CFG0
#define CYREG_B0_UDB04_A1
#define CYREG_B0_P6_U1_CFG18
#define CYREG_B1_UDB11_12_A1
#define CYREG_PICU6_INTTYPE5
#define CYREG_FLSHID_CUST_TABLES_CMP3_TR0_HS
#define CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM
#define CYREG_CAN0_TX3_DL
#define CYREG_B0_P6_U1_CFG5
#define CYREG_B0_P4_U1_CFG5
#define CYREG_USB_SIE_EP4_CNT0
#define CYREG_USB_USB_CLK_EN
#define CYREG_PHUB_TDMEM42_ORIG_TD1
#define CYREG_B1_P2_U0_PLD_IT1
#define CYREG_ROM_TABLE_DWT
#define CYREG_P3BA_ABSADDR1
#define CYREG_B1_P5_U1_CFG8
#define CYREG_B0_P6_U1_DCFG7
#define CYREG_DFB0_CSA_SRAM_DATA_MSIZE
#define CYREG_PHUB_TDMEM119_ORIG_TD0
#define CYREG_CAN0_TX2_ID
#define CYREG_PICU6_INTTYPE2
#define CYREG_FLSHID_CUST_TABLES_DEC_M5
#define CYREG_B0_P5_U0_CFG11
#define CYREG_B0_P1_U1_MC_CFG_BYPASS
#define CYREG_PHUB_TDMEM86_ORIG_TD0
#define CYREG_CLKDIST_WRK0
#define CYREG_PM_ACT_CFG3
#define CYREG_PHUB_ERR_ADR
#define CYREG_B0_P7_U1_DCFG7
#define CYREG_DFB0_DALIGN
#define CYREG_CAN0_TX2_DH
#define CYREG_DMA_SRAM32K_MSIZE
#define CYREG_CLKDIST_ACFG0_CFG2
#define CYREG_B1_UDB10_11_ST
#define CYREG_B0_P3_U1_DCFG2
#define CYREG_B0_UDB14_15_A0
#define CYREG_SRAM_DATA64K_MSIZE
#define CYREG_B1_UDB11_D1
#define CYREG_B0_P7_U1_CFG2
#define CYREG_B1_P2_U0_PLD_IT10
#define CYREG_B0_P4_U0_CFG16
#define CYREG_B0_UDB09_10_F1
#define CYREG_B0_P1_U0_MC_CFG_XORFB
#define CYREG_PHUB_CH0_BASIC_CFG
#define CYREG_B0_P4_U1_CFG19
#define CYREG_B1_UDB08_A1
#define CYREG_PHUB_CFGMEM12_CFG1
#define CYREG_B0_P5_U0_CFG25
#define CYREG_CACHE_ECC_CORR
#define CYREG_PHUB_TDMEM122_ORIG_TD0
#define CYREG_B1_P3_U1_CFG19
#define CYREG_B1_P4_U0_CFG18
#define CYREG_B0_UDB11_12_ACTL
#define CYREG_B0_P1_U1_CFG14
#define CYREG_B1_P2_U1_CFG16
#define CYREG_PHUB_TDMEM45_ORIG_TD0
#define CYREG_PHUB_TDMEM88_ORIG_TD1
#define CYREG_USB_SIE_EP4_CR0
#define CYREG_B1_UDB10_MSK
#define CYREG_B0_UDB01_F0_F1
#define CYREG_B0_P4_U0_PLD_IT2
#define CYREG_NVIC_PRI_15
#define CYREG_B0_UDB11_D0
#define CYREG_PHUB_TDMEM93_ORIG_TD0
#define CYREG_B1_P2_U0_CFG0
#define CYREG_B1_P3_U1_PLD_IT6
#define CYREG_B1_UDB09_F1
#define CYREG_B0_UDB10_ACTL
#define CYREG_B0_P7_U0_CFG10
#define CYREG_P3BA_X_START2
#define CYREG_B0_P2_U0_CFG4
#define CYREG_BCTL0_DCLK_EN0
#define CYREG_PHUB_TDMEM90_ORIG_TD1
#define CYREG_PHUB_TDMEM110_ORIG_TD0
#define CYREG_B0_UDB00_01_D0
#define CYREG_PHUB_TDMEM104_ORIG_TD1
#define CYREG_B1_P5_U0_PLD_IT8
#define CYREG_B0_P2_U1_CFG4
#define CYREG_FLSHID_CUST_TABLES_DAC2_M6
#define CYREG_B0_P4_U1_CFG21
#define CYREG_B0_P4_U0_CFG4
#define CYREG_B1_UDB11_12_F1
#define CYREG_B0_UDB10_11_CTL
#define CYREG_PICU6_DISABLE_COR
#define CYREG_B0_P7_U1_CFG16
#define CYREG_B0_UDB12_ST_CTL
#define CYREG_B1_P5_U0_MC_CFG_SET_RESET
#define CYREG_PHUB_TDMEM23_ORIG_TD1
#define CYREG_USB_ARB_EP4_INT_EN
#define CYREG_B0_P2_U0_CFG16
#define CYREG_B0_P5_U0_CFG21
#define CYREG_B1_P5_U0_PLD_IT2
#define CYREG_B1_P4_U0_CFG31
#define CYREG_B1_UDB06_F1
#define CYREG_PHUB_TDMEM91_ORIG_TD1
#define CYREG_PM_ACT_CFG10
#define CYREG_PHUB_TDMEM18_ORIG_TD1
#define CYREG_PRT15_CAPS_SEL
#define CYREG_PHUB_TDMEM14_ORIG_TD1
#define CYREG_B0_UDB14_MC
#define CYREG_B0_P1_U1_CFG8
#define CYREG_PRT4_SYNC_OUT
#define CYREG_B1_UDB06_D0
#define CYREG_B0_UDB09_MC_00
#define CYREG_CLKDIST_ACFG2_CFG0
#define CYREG_PRT3_CAPS_SEL
#define CYREG_B0_P7_U1_PLD_IT9
#define CYREG_B0_P6_U1_PLD_IT10
#define CYREG_PRT3_LCD_EN
#define CYREG_PM_AVAIL_CR3
#define CYREG_PM_MODE_CSR
#define CYREG_B0_P7_U1_PLD_IT10
#define CYREG_B0_UDB04_ST
#define CYREG_B0_UDB11_12_CTL
#define CYREG_USB_ARB_RW3_DR
#define CYREG_B0_P3_U1_CFG26
#define CYREG_PHUB_CH3_ACTION
#define CYREG_B0_P3_U0_CFG4
#define CYREG_B0_P2_U0_CFG17
#define CYREG_PICU3_INTTYPE7
#define CYREG_PHUB_CFGMEM7_CFG1
#define CYREG_FPB_FP_COMP_2
#define CYREG_B0_P4_U1_CFG20
#define CYREG_B1_P2_U1_CFG27
#define CYREG_FLSHID_CUST_TABLES_DAC0_M7
#define CYREG_PHUB_TDMEM30_ORIG_TD1
#define CYREG_B0_UDB12_ACTL
#define CYREG_B0_UDB06_07_A1
#define CYREG_CLKDIST_ACFG1_CFG1
#define CYREG_TMR0_CNT_CMP0
#define CYREG_CLKDIST_ACFG2_CFG3
#define CYREG_PHUB_TDMEM112_ORIG_TD0
#define CYREG_B0_UDB12_ST
#define CYREG_B0_P6_U1_CFG19
#define CYREG_B0_P3_U0_CFG6
#define CYREG_PHUB_TDMEM127_ORIG_TD0
#define CYREG_B1_UDB07_A1
#define CYREG_B0_P1_U0_CFG28
#define CYREG_SFR_GPIO6_SEL
#define CYREG_CAN0_TX2_CMD
#define CYREG_PHUB_CFGMEM5_CFG0
#define CYREG_B1_P3_U0_CFG30
#define CYREG_PRT0_BIT_MASK
#define CYREG_B0_P1_U1_CFG17
#define CYREG_CACHE_FLASH_ERR
#define CYREG_SRAM_DATA16K_MBASE
#define CYREG_B0_P3_U1_CFG0
#define CYREG_B0_UDB13_F0
#define CYREG_B0_P3_U0_PLD_ORT3
#define CYREG_B0_P5_U1_CFG12
#define CYREG_CLKDIST_BCFG0
#define CYREG_B0_P4_U0_CFG9
#define CYREG_B0_P2_U0_CFG1
#define CYREG_B1_P2_U1_DCFG1
#define CYREG_B0_UDB14_ST_CTL
#define CYREG_B0_UDB06_07_ACTL
#define CYREG_B1_P2_U1_PLD_IT7
#define CYREG_B0_P4_U1_CFG8
#define CYREG_B1_P5_U1_DCFG6
#define CYREG_CLKDIST_DCFG2_CFG0
#define CYREG_CAN0_RX14_DH
#define CYREG_B0_P5_U1_CFG2
#define CYREG_B0_P7_U0_CFG1
#define CYREG_PHUB_CH4_BASIC_STATUS
#define CYREG_PRT12_SIO_REG_HIFREQ
#define CYREG_USB_EP0_DR2
#define CYREG_B0_P5_U0_PLD_IT4
#define CYREG_FLASH_DATA_MBASE
#define CYREG_PHUB_TDMEM17_ORIG_TD1
#define CYREG_B0_UDB05_06_F1
#define CYREG_PHUB_TDMEM27_ORIG_TD1
#define CYREG_CAN0_RX15_AMRD
#define CYREG_B1_UDB05_06_CTL
#define CYREG_FLSHID_CUST_TABLES_DAC3_M2
#define CYREG_B1_UDB04_A0_A1
#define CYREG_B0_P2_U1_PLD_ORT2
#define CYREG_B0_P5_U1_CFG31
#define CYREG_B0_P5_U1_DCFG0
#define CYREG_CAN0_TX4_ID
#define CYREG_B0_P7_U0_CFG31
#define CYREG_B0_P7_U0_CFG17
#define CYREG_CLKDIST_DCFG5_CFG1
#define CYREG_B1_P2_U1_PLD_IT10
#define CYREG_B0_P4_U1_DCFG1
#define CYREG_B1_P3_U0_CFG1
#define CYREG_PM_ACT_CFG0
#define CYREG_B0_UDB08_09_A1
#define CYREG_CAN0_RX15_ID
#define CYREG_PHUB_TDMEM54_ORIG_TD0
#define CYREG_PHUB_TDMEM7_ORIG_TD1
#define CYREG_PHUB_CH5_BASIC_CFG
#define CYREG_DWT_FUNCTION_3
#define CYREG_CACHE_HITMISS
#define CYREG_B0_P3_U0_PLD_IT1
#define CYREG_ETM_AUTH_STATUS
#define CYREG_B0_UDB09_D0
#define CYREG_B0_P0_U0_CFG27
#define CYREG_B0_P1_U0_DCFG3
#define CYREG_B0_P1_U0_CFG14
#define CYREG_B1_P5_U0_DCFG2
#define CYREG_IO_PC_PRT15_PC0
#define CYREG_B1_P3_U0_PLD_ORT3
#define CYREG_B0_P7_U0_CFG8
#define CYREG_B1_UDB08_09_A0
#define CYREG_B1_P3_U1_CFG2
#define CYREG_USB_SIE_EP7_CNT0
#define CYREG_CAN0_RX4_DL
#define CYREG_PHUB_TDMEM92_ORIG_TD1
#define CYREG_B0_UDB05_MC_00
#define CYREG_PRT6_PS_ALIAS
#define CYREG_PHUB_CH23_ACTION
#define CYREG_PHUB_TDMEM123_ORIG_TD0
#define CYREG_B0_P1_U1_DCFG6
#define CYREG_B0_P3_U1_CFG19
#define CYREG_PM_AVAIL_CR1
#define CYREG_B0_P0_U1_CFG1
#define CYREG_B0_P3_U1_PLD_IT10
#define CYREG_PHUB_CH16_BASIC_STATUS
#define CYREG_B1_UDB07_08_ST
#define CYREG_B0_P7_U1_CFG13
#define CYREG_B1_P3_U1_DCFG7
#define CYREG_CAN0_TX6_CMD
#define CYREG_B0_P7_U0_CFG28
#define CYREG_B1_P4_U1_CFG4
#define CYREG_PANTHER_CM3_LCKRST_STAT
#define CYREG_PHUB_TDMEM92_ORIG_TD0
#define CYREG_B1_P2_U0_CFG12
#define CYREG_B0_P4_U1_PLD_IT6
#define CYREG_PHUB_TDMEM121_ORIG_TD0
#define CYREG_SFR_GPIO5_SEL
#define CYREG_PHUB_TDMEM25_ORIG_TD1
#define CYREG_B1_P4_U1_CFG31
#define CYREG_PHUB_TDMEM109_ORIG_TD0
#define CYREG_B0_UDB11_12_D0
#define CYREG_B0_UDB07_08_MC
#define CYREG_PHUB_CFGMEM19_CFG1
#define CYREG_BCTL0_BCLK_EN3
#define CYREG_B0_P5_U1_PLD_IT4
#define CYREG_DFB0_DPB_SRAM_DATA_MSIZE
#define CYREG_B1_P5_U0_CFG31
#define CYREG_PRT2_SYNC_OUT
#define CYREG_NVIC_PRI_10
#define CYREG_PHUB_TDMEM4_ORIG_TD1
#define CYREG_B0_P6_U0_DCFG4
#define CYREG_B0_P3_U1_PLD_ORT3
#define CYREG_USB_ARB_INT_SR
#define CYREG_B1_P2_U1_CFG2
#define CYREG_B1_P4_U1_PLD_IT6
#define CYREG_B1_P3_U1_CFG5
#define CYREG_B0_P6_U0_PLD_IT10
#define CYREG_B0_P3_U1_PLD_IT9
#define CYREG_B0_P0_U0_PLD_IT6
#define CYREG_B0_UDB14_15_F0
#define CYREG_B0_UDB07_D0
#define CYREG_B0_P2_U0_DCFG1
#define CYREG_B1_UDB07_ST_CTL
#define CYREG_B1_P3_U0_CFG0
#define CYREG_B0_P3_U0_PLD_IT0
#define CYREG_B0_P2_U1_DCFG2
#define CYREG_USB_ARB_EP2_SR
#define CYREG_FASTCLK_PLL_SR
#define CYREG_B0_P4_U1_CFG26
#define CYREG_B1_UDB10_F1
#define CYREG_B0_P6_U1_PLD_IT11
#define CYREG_B0_UDB09_10_MSK
#define CYREG_PICU6_INTTYPE0
#define CYREG_B0_P1_U0_CFG16
#define CYREG_PHUB_TDMEM67_ORIG_TD0
#define CYREG_B0_UDB04_05_D0
#define CYREG_B1_UDB04_05_ST
#define CYREG_PICU3_DISABLE_COR
#define CYREG_PANTHER_TRACE_CFG
#define CYREG_B0_UDB06_07_MSK
#define CYREG_B1_UDB09_MC_00
#define CYREG_B1_P2_U0_CFG19
#define CYREG_B0_P1_U1_CFG24
#define CYREG_PHUB_TDMEM63_ORIG_TD1
#define CYREG_CLKDIST_BCFG2
#define CYREG_PHUB_TDMEM82_ORIG_TD0
#define CYREG_B1_UDB11_A0_A1
#define CYREG_PHUB_CH1_ACTION
#define CYREG_CAN0_RX15_ACR
#define CYREG_B0_UDB05_A0
#define CYREG_B0_UDB00_D0_D1
#define CYREG_SFR_GPIO0_SEL
#define CYREG_B0_UDB15_A1
#define CYREG_B0_P4_U1_CFG13
#define CYREG_PICU3_INTTYPE2
#define CYREG_B0_P6_U1_DCFG5
#define CYREG_B0_P7_U0_DCFG1
#define CYREG_B0_P4_U0_PLD_IT9
#define CYREG_B0_P4_U0_DCFG1
#define CYREG_PHUB_TDMEM44_ORIG_TD0
#define CYREG_PRT5_OE_SEL1
#define CYREG_PHUB_TDMEM118_ORIG_TD0
#define CYREG_PICU2_INTTYPE1
#define CYREG_PHUB_CH1_BASIC_CFG
#define CYREG_CAN0_RX8_CMD
#define CYREG_PHUB_CH13_BASIC_CFG
#define CYREG_B0_P2_U1_CFG24
#define CYREG_PHUB_CH6_ACTION
#define CYREG_PHUB_CFGMEM13_CFG0
#define CYREG_B1_UDB08_D1
#define CYREG_B0_P6_U1_DCFG3
#define CYREG_B0_P2_U0_PLD_IT9
#define CYREG_B0_UDB12_13_D1
#define CYREG_B1_P5_U0_PLD_IT7
#define CYREG_PANTHER_DBG_CFG
#define CYREG_USB_DMA_THRES_MSB
#define CYREG_ROM_TABLE_END
#define CYREG_PHUB_CH9_ACTION
#define CYREG_NVIC_PRI_25
#define CYREG_B0_P0_U1_CFG17
#define CYREG_B0_P7_U0_CFG18
#define CYREG_PICU6_INTTYPE3
#define CYREG_B0_P4_U1_CFG10
#define CYREG_FASTCLK_PLL_P
#define CYREG_B1_P5_U1_MC_CFG_CEN_CONST
#define CYREG_B0_P2_U1_PLD_IT0
#define CYREG_B1_P3_U1_DCFG1
#define CYREG_CAN0_RX3_DL
#define CYREG_PHUB_CFGMEM16_CFG1
#define CYREG_B0_P3_U0_CFG24
#define CYREG_CAN0_RX2_ID
#define CYREG_NVIC_APPLN_INTR
#define CYREG_PRT3_BIT_MASK
#define CYREG_B1_P2_U1_PLD_IT0
#define CYREG_B0_P4_U0_CFG17
#define CYREG_B0_P0_U1_PLD_ORT3
#define CYREG_PHUB_CFGMEM2_CFG1
#define CYREG_B0_UDB09_A0
#define CYREG_CAN0_RX5_DH
#define CYREG_B0_P3_U0_DCFG7
#define CYREG_B1_P4_U0_PLD_IT11
#define CYREG_PHUB_CH22_ACTION
#define CYREG_B0_P0_U1_MC_CFG_SET_RESET
#define CYREG_P3BA_OFFSETADDR2
#define CYREG_B1_UDB04_A1
#define CYREG_B0_P4_U1_CFG15
#define CYREG_B0_P3_U0_CFG18
#define CYREG_B1_P5_U0_CFG2
#define CYREG_B1_UDB09_F0_F1
#define CYREG_B0_P3_U0_CFG19
#define CYREG_B0_P0_U1_PLD_IT1
#define CYREG_B0_UDB08_A0
#define CYREG_PHUB_TDMEM106_ORIG_TD0
#define CYREG_B1_P5_U0_PLD_IT1
#define CYREG_B0_UDB12_F0_F1
#define CYREG_B0_P5_U0_CFG9
#define CYREG_B1_P2_U0_PLD_ORT2
#define CYREG_B1_P2_U0_PLD_IT4
#define CYREG_CAN0_RX2_CMD
#define CYREG_B1_P4_U0_CFG3
#define CYREG_B0_P0_U1_PLD_IT9
#define CYREG_PRT3_OUT_SEL1
#define CYREG_P3BA_PHUB_MASTER_SSR
#define CYREG_B1_UDB04_D1
#define CYREG_B1_P5_U0_DCFG5
#define CYREG_B0_UDB04_05_ACTL
#define CYREG_B1_UDB11_F0_F1
#define CYREG_B1_P2_U0_DCFG6
#define CYREG_B0_P5_U1_PLD_IT11
#define CYREG_USB_EP0_DR1
#define CYREG_B0_P0_U0_DCFG1
#define CYREG_B1_P4_U0_PLD_IT3
#define CYREG_B1_P4_U0_PLD_IT6
#define CYREG_B0_P2_U1_PLD_IT3
#define CYREG_USB_SIE_EP8_CR0
#define CYREG_B1_UDB07_D1
#define CYREG_B0_P3_U0_CFG28
#define CYREG_FLSHID_CUST_TABLES_IMO_67MHZ
#define CYREG_TPIU_FORM_FLUSH_CTRL
#define CYREG_B1_UDB10_F0_F1
#define CYREG_B0_UDB14_D1
#define CYREG_B1_UDB05_06_D0
#define CYREG_PM_AVAIL_SR0
#define CYREG_B0_UDB08_MSK_ACTL
#define CYREG_B0_UDB00_01_MC
#define CYREG_B0_P1_U0_PLD_ORT1
#define CYREG_B0_P1_U0_CFG29
#define CYREG_B1_P4_U0_PLD_ORT2
#define CYREG_IO_PC_PRT15_PC1
#define CYREG_B0_P2_U1_CFG3
#define CYREG_B1_UDB04_ST_CTL
#define CYREG_ROM_TABLE_CID2
#define CYREG_FLSECC_DATA_MSIZE
#define CYREG_B0_UDB02_03_F1
#define CYREG_USB_ARB_RW2_RA
#define CYREG_BCTL1_MDCLK_EN
#define CYREG_TMR2_CNT_CMP0
#define CYREG_B0_P7_U0_PLD_IT10
#define CYREG_PHUB_TDMEM69_ORIG_TD0
#define CYREG_B0_P4_U0_CFG19
#define CYREG_B1_P4_U0_CFG5
#define CYREG_USB_SIE_EP2_CR0
#define CYREG_B0_P0_U0_DCFG7
#define CYREG_B0_P5_U1_MC_CFG_SET_RESET
#define CYREG_PM_ACT_CFG6
#define CYREG_CAN0_RX9_AMRD
#define CYREG_PICU2_INTTYPE4
#define CYREG_BCTL0_DCLK_EN3
#define CYREG_SRAM_DATA32K_MBASE
#define CYREG_B0_P1_U1_PLD_ORT2
#define CYREG_PM_STBY_CFG9
#define CYREG_PHUB_TDMEM69_ORIG_TD1
#define CYREG_B0_P7_U1_PLD_IT5
#define CYREG_B0_P2_U1_DCFG7
#define CYREG_B1_P4_U0_CFG24
#define CYREG_PHUB_TDMEM62_ORIG_TD0
#define CYREG_B0_UDB07_D0_D1
#define CYREG_B1_UDB06_07_D0
#define CYREG_PRT6_OUT_SEL1
#define CYREG_PHUB_TDMEM64_ORIG_TD0
#define CYREG_B1_P3_U1_DCFG2
#define CYREG_PHUB_TDMEM12_ORIG_TD0
#define CYREG_B0_UDB02_03_ACTL
#define CYREG_B0_P5_U0_PLD_IT1
#define CYREG_B0_P6_U0_MC_CFG_CEN_CONST
#define CYREG_B0_UDB02_03_A0
#define CYREG_B1_P2_U0_CFG30
#define CYREG_B0_P1_U1_CFG5
#define CYREG_PRT3_DBL_SYNC_IN
#define CYREG_B0_P6_U0_DCFG3
#define CYREG_PICU15_INTTYPE5
#define CYREG_PICU0_INTTYPE0
#define CYREG_B0_P4_U0_CFG30
#define CYREG_PICU12_INTTYPE6
#define CYREG_B0_P5_U0_CFG2
#define CYREG_ROM_TABLE_CID1
#define CYREG_B1_P2_U0_CFG31
#define CYREG_B0_UDB08_F0_F1
#define CYREG_FLSHID_CUST_TABLES_DAC0_M1
#define CYREG_B1_UDB11_12_CTL
#define CYREG_B0_P7_U1_CFG26
#define CYREG_B0_P5_U1_CFG16
#define CYREG_B0_P4_U0_PLD_IT3
#define CYREG_CAN0_TX1_ID
#define CYREG_PHUB_CH17_BASIC_CFG
#define CYREG_B0_UDB11_F1
#define CYREG_DFB0_RAM_DIR
#define CYREG_B0_P6_U0_PLD_IT5
#define CYREG_B1_UDB07_MSK_ACTL
#define CYREG_P3BA_EXP_DATA3
#define CYREG_B1_UDB09_10_A1
#define CYREG_B1_UDB06_D0_D1
#define CYREG_NVIC_USAGE_FAULT_STATUS
#define CYREG_B1_P5_U1_MC_CFG_SET_RESET
#define CYREG_CLKDIST_DCFG2_CFG1
#define CYREG_USB_ARB_RW5_DR
#define CYREG_B0_UDB12_MSK_ACTL
#define CYREG_PHUB_TDMEM31_ORIG_TD0
#define CYREG_B0_UDB07_F0_F1
#define CYREG_B1_UDB07_ACTL
#define CYREG_PM_STBY_CFG11
#define CYREG_PHUB_TDMEM17_ORIG_TD0
#define CYREG_B1_P4_U0_DCFG4
#define CYREG_CAN0_RX3_CMD
#define CYREG_PRT2_DR_ALIAS
#define CYREG_B0_UDB08_09_MSK
#define CYREG_PICU1_INTTYPE4
#define CYREG_B0_P6_U0_PLD_IT2
#define CYREG_DFB0_CSA_SRAM_DATA_MBASE
#define CYREG_B1_UDB04_CTL
#define CYREG_B1_UDB11_12_ACTL
#define CYREG_B0_P7_U1_PLD_IT11
#define CYREG_PHUB_CH21_BASIC_CFG
#define CYREG_B1_P3_U1_CFG18
#define CYREG_CAN0_RX5_ACR
#define CYREG_B0_UDB09_D1
#define CYREG_PHUB_TDMEM49_ORIG_TD0
#define CYREG_PHUB_CFGMEM18_CFG1
#define CYREG_B0_UDB10_CTL
#define CYREG_B0_UDB07_08_F1
#define CYREG_B1_P5_U1_CFG17
#define CYREG_PRT5_DR_ALIAS
#define CYREG_B0_P4_U1_CFG23
#define CYREG_B1_P5_U1_PLD_ORT2
#define CYREG_PHUB_TDMEM29_ORIG_TD0
#define CYREG_PRT4_OE_SEL1
#define CYREG_PRT5_DBL_SYNC_IN
#define CYREG_SFR_GPIO4_SEL
#define CYREG_B0_P7_U1_CFG7
#define CYREG_B1_P3_U1_CFG24
#define CYREG_SFR_GPIO2_SEL
#define CYREG_B0_UDB03_04_F1
#define CYREG_B0_P7_U1_CFG31
#define CYREG_DFB0_CSB_SRAM_DATA_MBASE
#define CYREG_B1_P4_U0_PLD_ORT0
#define CYREG_BCTL1_DCLK_EN0
#define CYREG_PICU1_INTTYPE7
#define CYREG_B0_P1_U1_DCFG5
#define CYREG_B0_P5_U0_CFG24
#define CYREG_B0_P5_U0_CFG8
#define CYREG_EMIF_RP_WAIT_STATES
#define CYREG_B0_P6_U0_CFG5
#define CYREG_DFB0_RAM_EN
#define CYREG_B0_P4_U1_CFG27
#define CYREG_PHUB_TDMEM72_ORIG_TD1
#define CYREG_PHUB_CFGMEM3_CFG0
#define CYREG_USB_ARB_RW3_RA
#define CYREG_B0_P5_U1_PLD_IT5
#define CYREG_B1_UDB10_ST
#define CYREG_B0_P6_U1_MC_CFG_CEN_CONST
#define CYREG_B0_UDB00_MC
#define CYREG_IDMUX_DRQ_CTL4
#define CYREG_B0_UDB14_MSK_ACTL
#define CYREG_B0_P7_U1_CFG18
#define CYREG_B0_UDB12_A0
#define CYREG_CAN0_CSR_ERR_SR
#define CYREG_B0_P4_U0_CFG18
#define CYREG_B1_UDB07_F0
#define CYREG_B0_UDB02_F0_F1
#define CYREG_PRT12_BIT_MASK
#define CYREG_B1_UDB08_09_ACTL
#define CYREG_B0_P0_U0_CFG26
#define CYREG_PHUB_CH16_BASIC_CFG
#define CYREG_B1_UDB06_07_F1
#define CYREG_B0_UDB11_ACTL
#define CYREG_B0_UDB07_A0
#define CYREG_B1_UDB05_D0
#define CYREG_B0_P7_U0_DCFG5
#define CYREG_PHUB_CH8_BASIC_CFG
#define CYREG_PICU4_INTSTAT
#define CYREG_USB_ARB_RW6_RA
#define CYREG_PHUB_TDMEM51_ORIG_TD0
#define CYREG_B0_P4_U1_MC_CFG_SET_RESET
#define CYREG_B0_P0_U1_CFG31
#define CYREG_B0_P0_U1_CFG15
#define CYREG_PICU15_INTTYPE0
#define CYREG_B1_P2_U1_CFG3
#define CYREG_B1_P4_U1_PLD_ORT2
#define CYREG_B0_P1_U1_CFG19
#define CYREG_FASTCLK_XMHZ_CSR
#define CYREG_DFB0_HOLDBM
#define CYREG_B0_P2_U0_CFG28
#define CYREG_PHUB_CFGMEM16_CFG0
#define CYREG_B0_UDB04_ST_CTL
#define CYREG_B0_P7_U0_CFG2
#define CYREG_B0_P4_U1_PLD_IT0
#define CYREG_B1_P3_U0_CFG23
#define CYREG_B0_P4_U0_PLD_IT8
#define CYREG_B0_UDB00_01_F1
#define CYREG_B0_P5_U1_DCFG5
#define CYREG_B0_P4_U0_PLD_IT0
#define CYREG_B0_UDB08_CTL
#define CYREG_CAN0_RX0_AMR
#define CYREG_B0_P3_U0_PLD_IT4
#define CYREG_B0_P7_U0_CFG29
#define CYREG_B0_P5_U1_CFG30
#define CYREG_FLSHID_CUST_TABLES_DAC0_M2
#define CYREG_B0_P1_U0_PLD_IT5
#define CYREG_B1_P4_U1_MC_CFG_XORFB
#define CYREG_PHUB_TDMEM87_ORIG_TD1
#define CYREG_USB_SIE_EP_INT_SR
#define CYREG_PHUB_CH13_BASIC_STATUS
#define CYREG_B0_P5_U0_CFG20
#define CYREG_ETM_INT_MODE_CTRL
#define CYREG_B0_UDB01_MSK_ACTL
#define CYREG_B1_P4_U0_PLD_ORT1
#define CYREG_B0_P6_U1_CFG8
#define CYREG_B0_P1_U1_CFG22
#define CYREG_B0_P4_U0_DCFG3
#define CYREG_B0_UDB04_05_F1
#define CYREG_B0_P5_U0_CFG22
#define CYREG_B0_UDB13_14_CTL
#define CYREG_B1_UDB09_MC
#define CYREG_PRT15_OUT_SEL1
#define CYREG_PHUB_TDMEM55_ORIG_TD0
#define CYREG_B1_UDB09_A0
#define CYREG_B0_P1_U1_CFG20
#define CYREG_NVIC_PRI_21
#define CYREG_CAN0_RX0_DL
#define CYREG_B0_P5_U0_CFG10
#define CYREG_B0_P6_U1_PLD_IT1
#define CYREG_B1_P5_U0_CFG14
#define CYREG_CAN0_RX11_ID
#define CYREG_DWT_SLEEP_COUNT
#define CYREG_CLKDIST_DLY1
#define CYREG_PHUB_TDMEM14_ORIG_TD0
#define CYREG_PICU4_INTTYPE4
#define CYREG_P3BA_XROLL1
#define CYREG_I2C_CLK_DIV2
#define CYREG_B1_UDB05_MC
#define CYREG_B0_UDB05_A1
#define CYREG_PHUB_CH13_ACTION
#define CYREG_PHUB_CFGMEM20_CFG1
#define CYREG_B0_P5_U1_PLD_ORT3
#define CYREG_PHUB_TDMEM23_ORIG_TD0
#define CYREG_CAN0_RX11_DH
#define CYREG_B1_UDB06_07_ACTL
#define CYREG_B0_P6_U0_CFG4
#define CYREG_PHUB_TDMEM37_ORIG_TD0
#define CYREG_CAN0_RX4_AMR
#define CYREG_PHUB_TDMEM56_ORIG_TD1
#define CYREG_B0_P3_U1_CFG15
#define CYREG_B0_P3_U0_PLD_IT3
#define CYREG_B1_P3_U1_CFG8
#define CYREG_B0_P6_U1_CFG2
#define CYREG_CAN0_TX1_DL
#define CYREG_B0_UDB07_08_F0
#define CYREG_PICU12_INTTYPE7
#define CYREG_PHUB_TDMEM63_ORIG_TD0
#define CYREG_B0_UDB09_10_D1
#define CYREG_B1_UDB11_F1
#define CYREG_PICU3_INTTYPE5
#define CYREG_B0_UDB12_13_A0
#define CYREG_PRT15_INP_DIS
#define CYREG_USB_DMA_THRES
#define CYREG_B0_UDB04_A0
#define CYREG_B0_P3_U1_CFG12
#define CYREG_B1_P4_U0_CFG23
#define CYREG_PHUB_TDMEM100_ORIG_TD1
#define CYREG_PHUB_TDMEM46_ORIG_TD1
#define CYREG_B0_P3_U1_DCFG7
#define CYREG_ANAIF_WRK_SARS_SOF
#define CYREG_B0_UDB05_06_A0
#define CYREG_B0_UDB13_14_F1
#define CYREG_B0_UDB03_04_D1
#define CYREG_B0_UDB15_A0
#define CYREG_B0_P0_U1_CFG28
#define CYREG_B0_P6_U1_PLD_IT3
#define CYREG_B0_P3_U1_CFG24
#define CYREG_ROM_TABLE_TPIU
#define CYREG_B0_P4_U1_CFG31
#define CYREG_B1_UDB10_D0_D1
#define CYREG_B0_UDB05_06_MC
#define CYREG_B1_UDB10_11_D0
#define CYREG_PHUB_TDMEM57_ORIG_TD1
#define CYREG_PHUB_TDMEM28_ORIG_TD1
#define CYREG_PHUB_TDMEM108_ORIG_TD1
#define CYREG_B0_P0_U1_PLD_IT8
#define CYREG_B0_UDB12_13_A1
#define CYREG_B0_P5_U1_PLD_IT8
#define CYREG_B0_P7_U0_PLD_IT0
#define CYREG_PHUB_TDMEM3_ORIG_TD1
#define CYREG_B1_UDB04_05_MC
#define CYREG_PHUB_TDMEM22_ORIG_TD1
#define CYREG_PHUB_TDMEM81_ORIG_TD0
#define CYREG_B1_P4_U1_PLD_IT5
#define CYREG_B0_UDB09_10_A0
#define CYREG_B0_UDB00_ACTL
#define CYREG_B0_UDB15_ST
#define CYREG_CAN0_RX10_CMD
#define CYREG_B0_UDB09_ST_CTL
#define CYREG_B0_P5_U0_CFG23
#define CYREG_B0_UDB06_D0_D1
#define CYREG_B0_P7_U1_PLD_ORT0
#define CYREG_PRT3_OUT_SEL0
#define CYREG_B1_P5_U1_PLD_IT3
#define CYREG_USB_ARB_EP6_INT_EN
#define CYREG_PRT15_DBL_SYNC_IN
#define CYREG_DEC_OUTSAMPM
#define CYREG_B0_UDB07_ST_CTL
#define CYREG_B1_P3_U1_PLD_IT7
#define CYREG_PRT4_OUT_SEL1
#define CYREG_B1_UDB04_F0
#define CYREG_B1_P5_U0_CFG25
#define CYREG_PHUB_TDMEM80_ORIG_TD0
#define CYREG_B0_P1_U1_CFG7
#define CYREG_B0_P0_U1_PLD_ORT2
#define CYREG_PRT1_LCD_COM_SEG
#define CYREG_CAN0_RX15_DL
#define CYREG_B0_P7_U0_CFG22
#define CYREG_B0_P3_U1_CFG28
#define CYREG_B0_P2_U1_CFG20
#define CYREG_B1_P2_U1_DCFG4
#define CYREG_B0_P0_U0_CFG31
#define CYREG_B1_UDB09_10_MSK
#define CYREG_B0_P5_U1_MC_CFG_BYPASS
#define CYREG_B0_P4_U0_DCFG0
#define CYREG_CAN0_RX7_DH
#define CYREG_B0_P7_U0_CFG12
#define CYREG_B0_P2_U1_CFG31
#define CYREG_B0_P0_U0_PLD_ORT1
#define CYREG_B1_UDB08_09_ST
#define CYREG_PHUB_TDMEM88_ORIG_TD0
#define CYREG_PHUB_CH0_BASIC_STATUS
#define CYREG_PICU1_INTTYPE2
#define CYREG_PRT0_INP_DIS
#define CYREG_PHUB_TDMEM8_ORIG_TD0
#define CYREG_CLKDIST_ACFG3_CFG0
#define CYREG_B1_P2_U1_MC_CFG_SET_RESET
#define CYREG_B1_UDB11_ACTL
#define CYREG_B0_UDB12_F0
#define CYREG_PHUB_TDMEM100_ORIG_TD0
#define CYREG_CAN0_RX8_AMR
#define CYREG_USB_ARB_RW8_WA_MSB
#define CYREG_B0_P3_U1_DCFG3
#define CYREG_B1_P3_U1_PLD_IT2
#define CYREG_B0_UDB10_A0_A1
#define CYREG_USB_BUS_RST_CNT
#define CYREG_PHUB_TDMEM9_ORIG_TD1
#define CYREG_B1_UDB04_05_A0
#define CYREG_B1_P3_U1_PLD_IT0
#define CYREG_B0_P5_U0_MC_CFG_XORFB
#define CYREG_USB_ARB_EP6_CFG
#define CYREG_B1_P3_U1_CFG3
#define CYREG_P3BA_OFFSETADDR3
#define CYREG_CAN0_RX4_AMRD
#define CYREG_P3BA_DATA_REG3
#define CYREG_B0_P6_U0_PLD_IT7
#define CYREG_B0_P0_U0_DCFG4
#define CYREG_B0_P6_U0_PLD_IT9
#define CYREG_B1_P3_U1_PLD_ORT1
#define CYREG_NVIC_SYS_PRIO_HANDLER_8_11
#define CYREG_PHUB_TDMEM1_ORIG_TD0
#define CYREG_B1_UDB04_MSK
#define CYREG_CAN0_RX11_AMR
#define CYREG_B0_P7_U0_PLD_ORT1
#define CYREG_B0_P2_U0_CFG11
#define CYREG_B0_UDB15_ST_CTL
#define CYREG_FLSHID_CUST_TABLES_DAC1_M8
#define CYREG_B0_UDB02_A1
#define CYREG_CAN0_TX6_ID
#define CYREG_B1_P5_U1_DCFG1
#define CYREG_B0_P6_U0_PLD_IT3
#define CYREG_PHUB_TDMEM83_ORIG_TD1
#define CYREG_FLSHID_CUST_TABLES_DAC3_M7
#define CYREG_B0_P4_U1_PLD_IT5
#define CYREG_B0_P5_U0_DCFG1
#define CYREG_NVIC_PRI_31
#define CYREG_B0_UDB14_15_D0
#define CYREG_B0_P2_U0_PLD_ORT3
#define CYREG_ETM_TR_SS_EMBICE_CTRL
#define CYREG_B0_UDB08_A0_A1
#define CYREG_B0_UDB13_MSK_ACTL
#define CYREG_PRT3_SYNC_OUT
#define CYREG_B1_UDB10_F0
#define CYREG_PHUB_CH10_BASIC_CFG
#define CYREG_B0_UDB09_10_CTL
#define CYREG_PHUB_CFGMEM14_CFG1
#define CYREG_B0_UDB01_02_ST
#define CYREG_CAN0_RX12_DH
#define CYREG_B0_P1_U0_CFG15
#define CYREG_USB_EP0_CNT
#define CYREG_B0_P3_U1_CFG23
#define CYREG_IO_PC_PRT15_PC2
#define CYREG_B0_UDB09_10_ACTL
#define CYREG_PRT12_OUT_SEL1
#define CYREG_B1_P3_U0_PLD_IT1
#define CYREG_B0_P2_U0_CFG6
#define CYREG_PHUB_CH3_BASIC_STATUS
#define CYREG_B0_P3_U1_PLD_ORT0
#define CYREG_B0_UDB09_ACTL
#define CYREG_B0_UDB13_ACTL
#define CYREG_B0_UDB03_F0
#define CYREG_B1_UDB09_MSK_ACTL
#define CYREG_USB_CWA_MSB
#define CYREG_PHUB_TDMEM47_ORIG_TD0
#define CYREG_CAN0_RX8_DL
#define CYREG_B1_UDB07_08_ACTL
#define CYREG_B1_P4_U1_CFG25
#define CYREG_B1_P5_U1_CFG12
#define CYREG_B1_UDB11_MSK
#define CYREG_PWRSYS_WAKE_TR0
#define CYREG_B1_UDB08_MSK_ACTL
#define CYREG_B0_P6_U0_CFG7
#define CYREG_B0_P3_U1_CFG17
#define CYREG_B0_P2_U1_DCFG3
#define CYREG_B0_P6_U0_PLD_IT4
#define CYREG_USB_ARB_EP3_INT_EN
#define CYREG_B0_P0_U0_CFG12
#define CYREG_USB_ARB_EP8_SR
#define CYREG_B0_P1_U1_CFG26
#define CYREG_PHUB_CH6_BASIC_CFG
#define CYREG_B0_P1_U0_CFG22
#define CYREG_B1_UDB06_A0
#define CYREG_B1_P5_U0_CFG15
#define CYREG_B0_P5_U0_PLD_IT7
#define CYREG_B0_UDB03_MC_00
#define CYREG_B1_P2_U1_MC_CFG_XORFB
#define CYREG_PHUB_TDMEM76_ORIG_TD1
#define CYREG_EMIF_EM_TYPE
#define CYREG_B1_UDB10_CTL
#define CYREG_TMR2_CNT_CMP1
#define CYREG_B0_P0_U0_CFG29
#define CYREG_B1_P2_U0_DCFG0
#define CYREG_FLSHID_CUST_TABLES_DEC_M1
#define CYREG_PHUB_TDMEM109_ORIG_TD1
#define CYREG_NVIC_PRI_29
#define CYREG_B0_P0_U0_CFG23
#define CYREG_B0_UDB02_03_D1
#define CYREG_B0_P1_U0_DCFG5
#define CYREG_B1_P2_U1_CFG26
#define CYREG_B1_P5_U0_CFG26
#define CYREG_NVIC_SYSTICK_CURRENT
#define CYREG_USB_ARB_CFG
#define CYREG_NVIC_MEMMAN_FAULT_ADD
#define CYREG_B0_P3_U1_MC_CFG_CEN_CONST
#define CYREG_B0_P7_U0_CFG24
#define CYREG_ITM_TRACE_EN
#define CYREG_B1_P3_U0_CFG8
#define CYREG_B0_P7_U0_PLD_IT7
#define CYREG_CAN0_TX4_DL
#define CYREG_PRT2_LCD_EN
#define CYREG_CLKDIST_DCFG0_CFG1
#define CYREG_B0_UDB14_D0_D1
#define CYREG_PHUB_CH8_BASIC_STATUS
#define CYREG_PRT1_INP_DIS
#define CYREG_CAN0_RX8_AMRD
#define CYREG_B1_P3_U0_CFG24
#define CYREG_CLKDIST_DCFG5_CFG2
#define CYREG_ITM_LOCK_STATUS
#define CYREG_PWRSYS_I2C_TR
#define CYREG_B1_UDB07_CTL
#define CYREG_PHUB_TDMEM103_ORIG_TD0
#define CYREG_B0_P1_U0_CFG0
#define CYREG_B0_P0_U1_CFG6
#define CYREG_B1_UDB08_09_MC
#define CYREG_PRT1_DR_ALIAS
#define CYREG_B0_UDB14_15_CTL
#define CYREG_B0_P7_U1_CFG15
#define CYREG_FLSHID_CUST_TABLES_DAC3_M3
#define CYREG_ROM_TABLE_PID7
#define CYREG_B0_UDB11_ST_CTL
#define CYREG_B0_UDB01_02_F1
#define CYREG_B1_P5_U0_CFG10
#define CYREG_B1_P3_U1_CFG11
#define CYREG_B1_UDB04_05_CTL
#define CYREG_B0_P2_U0_DCFG0
#define CYREG_PHUB_TDMEM2_ORIG_TD0
#define CYREG_B0_P0_U1_CFG18
#define CYREG_FLSHID_CUST_TABLES_IMO_6MHZ
#define CYREG_B0_P2_U0_CFG27
#define CYREG_PRT12_SIO_DIFF
#define CYREG_CAN0_RX9_AMR
#define CYREG_DFB0_STAGEAH
#define CYREG_NVIC_PRI_23
#define CYREG_PHUB_TDMEM110_ORIG_TD1
#define CYREG_B0_UDB01_MSK
#define CYREG_PHUB_TDMEM78_ORIG_TD1
#define CYREG_B1_P4_U1_CFG24
#define CYREG_B0_UDB05_06_ST
#define CYREG_B0_UDB09_F1
#define CYREG_B1_UDB09_ST
#define CYREG_PRT15_LCD_EN
#define CYREG_SPC_DMM_MAP_SRAM_MBASE
#define CYREG_B0_UDB14_F0_F1
#define CYREG_B0_P3_U1_CFG4
#define CYREG_PICU3_INTTYPE3
#define CYREG_B0_P4_U1_CFG14
#define CYREG_CAN0_RX1_AMR
#define CYREG_USB_ARB_EP3_CFG
#define CYREG_PHUB_TDMEM102_ORIG_TD0
#define CYREG_B1_UDB07_MC_00
#define CYREG_B0_UDB08_MC
#define CYREG_NVIC_PRI_30
#define CYREG_CLKDIST_DCFG1_CFG0
#define CYREG_ETM_CFG_CODE_EXT
#define CYREG_PHUB_TDMEM42_ORIG_TD0
#define CYREG_FLSHID_CUST_TABLES_FAB_YR
#define CYREG_SPC_FM_EE_CR
#define CYREG_B1_UDB10_11_MSK
#define CYREG_B0_P0_U0_CFG10
#define CYREG_B1_P4_U1_CFG29
#define CYREG_B0_UDB00_01_CTL
#define CYREG_B1_P5_U1_CFG1
#define CYREG_B1_P5_U0_PLD_IT0
#define CYREG_PRT4_LCD_COM_SEG
#define CYREG_P3BA_DATA_REG2
#define CYREG_B1_P4_U0_MC_CFG_XORFB
#define CYREG_CAN0_RX12_DL
#define CYREG_B0_UDB01_MC_00
#define CYREG_CORE_DBG_EXC_MON_CTL
#define CYREG_PHUB_TDMEM31_ORIG_TD1
#define CYREG_B0_UDB05_06_ACTL
#define CYREG_DFB0_INT_CTRL
#define CYREG_CAN0_RX13_AMR
#define CYREG_B0_P3_U0_CFG5
#define CYREG_B1_P4_U1_PLD_ORT0
#define CYREG_B1_P4_U1_CFG1
#define CYREG_B0_P2_U0_CFG25
#define CYREG_B1_P2_U1_PLD_IT5
#define CYREG_B1_P2_U1_CFG5
#define CYREG_B0_P5_U1_CFG19
#define CYREG_B0_P5_U0_CFG5
#define CYREG_CAN0_RX2_ACR
#define CYREG_FLSHID_CUST_TABLES_DAC3_M5
#define CYREG_PRT1_PS_ALIAS
#define CYREG_B0_P3_U1_PLD_IT2
#define CYREG_B1_P5_U0_DCFG6
#define CYREG_B1_P5_U0_PLD_IT10
#define CYREG_B0_P6_U0_CFG6
#define CYREG_B1_P3_U1_MC_CFG_SET_RESET
#define CYREG_PICU6_INTTYPE7
#define CYREG_B1_P3_U1_CFG9
#define CYREG_B1_P4_U0_CFG13
#define CYREG_B0_P7_U1_CFG20
#define CYREG_PHUB_TDMEM35_ORIG_TD1
#define CYREG_PRT5_PS_ALIAS
#define CYREG_PHUB_CH10_ACTION
#define CYREG_B1_UDB08_09_F0
#define CYREG_B1_P5_U0_MC_CFG_CEN_CONST
#define CYREG_B0_P7_U0_PLD_IT5
#define CYREG_PHUB_TDMEM74_ORIG_TD0
#define CYREG_B0_P4_U0_DCFG4
#define CYREG_B0_UDB01_02_MC
#define CYREG_TMR3_CNT_CMP0
#define CYREG_PHUB_TDMEM62_ORIG_TD1
#define CYREG_PHUB_TDMEM50_ORIG_TD0
#define CYREG_B0_P6_U0_CFG29
#define CYREG_B1_P4_U0_PLD_IT0
#define CYREG_ETM_SYS_CFG
#define CYREG_B1_P5_U0_CFG19
#define CYREG_B0_UDB08_09_D1
#define CYREG_PHUB_TDMEM107_ORIG_TD0
#define CYREG_B0_P1_U1_PLD_IT6
#define CYREG_PHUB_TDMEM98_ORIG_TD0
#define CYREG_PHUB_TDMEM119_ORIG_TD1
#define CYREG_B0_P4_U0_CFG15
#define CYREG_PHUB_TDMEM15_ORIG_TD1
#define CYREG_B1_P5_U0_CFG30
#define CYREG_B0_P2_U1_CFG18
#define CYREG_B0_P6_U1_PLD_ORT2
#define CYREG_B0_UDB03_MC
#define CYREG_B0_P2_U0_PLD_IT0
#define CYREG_USB_ARB_RW4_RA_MSB
#define CYREG_B0_UDB06_A0
#define CYREG_B0_P2_U1_DCFG1
#define CYREG_B0_UDB08_F0
#define CYREG_B0_P7_U0_CFG15
#define CYREG_ROM_TABLE_PID6
#define CYREG_B1_P4_U1_CFG17
#define CYREG_P3BA_EXP_DATA4
#define CYREG_CAN0_RX6_AMRD
#define CYREG_B0_P6_U1_DCFG0
#define CYREG_B0_P2_U1_PLD_ORT0
#define CYREG_PICU0_INTTYPE2
#define CYREG_B0_UDB11_F0
#define CYREG_B0_P1_U0_PLD_IT2
#define CYREG_B0_UDB06_07_CTL
#define CYREG_B0_P7_U0_CFG30
#define CYREG_B0_UDB13_CTL
#define CYREG_B0_P1_U1_CFG10
#define CYREG_B0_P4_U1_PLD_ORT3
#define CYREG_B1_UDB06_07_F0
#define CYREG_B0_P4_U0_CFG8
#define CYREG_FLSHID_CUST_TABLES_DAC1_M2
#define CYREG_PHUB_TDMEM114_ORIG_TD1
#define CYREG_B1_P2_U1_DCFG0
#define CYREG_B0_UDB02_MSK_ACTL
#define CYREG_B0_P6_U0_CFG30
#define CYREG_B0_P0_U0_DCFG2
#define CYREG_B0_P3_U0_CFG20
#define CYREG_B0_P7_U0_PLD_IT6
#define CYREG_PRT15_OE_SEL0
#define CYREG_B0_P5_U0_CFG6
#define CYREG_B0_P3_U1_CFG5
#define CYREG_B0_P4_U1_PLD_IT2
#define CYREG_ETM_CS_TRACE_ID
#define CYREG_USB_ARB_EP5_INT_EN
#define CYREG_B0_P5_U0_PLD_IT2
#define CYREG_P3BA_ABSADDR4
#define CYREG_PRT12_OE_SEL1
#define CYREG_PHUB_TDMEM3_ORIG_TD0
#define CYREG_B1_UDB08_D0_D1
#define CYREG_B0_P1_U0_PLD_ORT0
#define CYREG_TPIU_ASYNC_CLK_PRESCALER
#define CYREG_CACHE_CC_CTL
#define CYREG_PHUB_CFGMEM21_CFG0
#define CYREG_PHUB_TDMEM90_ORIG_TD0
#define CYREG_B0_UDB00_D0
#define CYREG_B0_P7_U1_CFG28
#define CYREG_B0_P1_U0_CFG25
#define CYREG_B0_P0_U1_CFG13
#define CYREG_PHUB_TDMEM116_ORIG_TD0
#define CYREG_USB_BUF_SIZE
#define CYREG_B1_UDB09_10_F0
#define CYREG_B1_UDB04_MC_00
#define CYREG_B1_UDB11_D0
#define CYREG_B1_P4_U1_PLD_IT9
#define CYREG_IDMUX_DRQ_CTL2
#define CYREG_FLSHID_CUST_TABLES_DAC2_M2
#define CYREG_B0_P0_U1_DCFG1
#define CYREG_B0_UDB02_A0
#define CYREG_B0_P7_U0_PLD_IT8
#define CYREG_B0_UDB10_ST_CTL
#define CYREG_B0_P0_U0_PLD_IT1
#define CYREG_PICU4_INTTYPE5
#define CYREG_B0_P1_U0_PLD_ORT2
#define CYREG_B0_P0_U0_PLD_IT8
#define CYREG_B1_UDB07_MSK
#define CYREG_B0_P6_U0_DCFG6
#define CYREG_B0_P5_U1_PLD_ORT1
#define CYREG_B1_P3_U0_CFG12
#define CYREG_B0_UDB03_D0
#define CYREG_B0_P1_U0_CFG3
#define CYREG_B1_P5_U1_CFG13
#define CYREG_PICU1_INTTYPE0
#define CYREG_CAN0_TX6_DL
#define CYREG_B0_UDB09_A0_A1
#define CYREG_EMIF_CLOCK_EN
#define CYREG_B0_P6_U1_DCFG4
#define CYREG_B0_UDB14_F0
#define CYREG_USB_ARB_RW4_WA_MSB
#define CYREG_B0_P3_U0_CFG31
#define CYREG_B1_UDB04_05_D0
#define CYREG_B0_P0_U1_CFG27
#define CYREG_B0_P5_U1_PLD_ORT2
#define CYREG_PRT0_LCD_EN
#define CYREG_PHUB_TDMEM39_ORIG_TD0
#define CYREG_B0_P4_U1_CFG2
#define CYREG_B0_P2_U1_PLD_ORT1
#define CYREG_B0_P1_U0_PLD_IT9
#define CYREG_USB_SIE_EP6_CNT0
#define CYREG_B0_P7_U1_DCFG5
#define CYREG_B1_UDB07_08_D1
#define CYREG_B1_P4_U0_PLD_IT9
#define CYREG_CAN0_RX7_DL
#define CYREG_B0_P0_U1_PLD_IT10
#define CYREG_PHUB_TDMEM10_ORIG_TD1
#define CYREG_B1_P4_U0_CFG28
#define CYREG_B1_P2_U0_CFG17
#define CYREG_USB_ARB_RW7_DR
#define CYREG_CAN0_RX13_ID
#define CYREG_BCTL1_DCLK_EN1
#define CYREG_B0_P2_U1_DCFG6
#define CYREG_SRAM_CODE_MBASE
#define CYREG_CAN0_RX4_ACR
#define CYREG_B0_P6_U1_PLD_ORT0
#define CYREG_B0_UDB13_A1
#define CYREG_PHUB_CH4_BASIC_CFG
#define CYREG_PICU_15_SNAP_15
#define CYREG_PWRSYS_WAKE_TR2
#define CYREG_PHUB_CH1_BASIC_STATUS
#define CYREG_B0_P1_U0_CFG27
#define CYREG_B0_P6_U0_CFG15
#define CYREG_B0_P1_U1_CFG4
#define CYREG_B1_P3_U1_CFG29
#define CYREG_B1_P4_U0_MC_CFG_SET_RESET
#define CYREG_B1_UDB07_08_F0
#define CYREG_PHUB_CH19_BASIC_CFG
#define CYREG_NPUMP_SC_TR0
#define CYREG_PM_AVAIL_CR4
#define CYREG_B1_UDB07_MC
#define CYREG_B0_P6_U1_PLD_IT7
#define CYREG_B0_UDB07_ACTL
#define CYREG_B1_UDB11_F0
#define CYREG_PICU15_INTTYPE6
#define CYREG_B0_P0_U0_CFG6
#define CYREG_USB_EP0_DR5
#define CYREG_DMA_SRAM16K_MBASE
#define CYREG_B1_UDB06_07_CTL
#define CYREG_B0_P5_U0_DCFG4
#define CYREG_B0_P6_U1_CFG4
#define CYREG_B0_P4_U1_PLD_IT7
#define CYREG_B0_UDB01_A0
#define CYREG_PRT12_SYNC_OUT
#define CYREG_B0_P3_U0_CFG0
#define CYREG_CAN0_RX1_CMD
#define CYREG_B1_UDB08_ST_CTL
#define CYREG_B0_P5_U1_CFG8
#define CYREG_CLKDIST_ACFG1_CFG2
#define CYREG_PRT15_LCD_COM_SEG
#define CYREG_NVIC_PRI_20
#define CYREG_B1_P4_U0_PLD_IT8
#define CYREG_PHUB_CH21_ACTION
#define CYREG_ITM_TRACE_CTRL
#define CYREG_B0_P4_U1_CFG9
#define CYREG_B0_P6_U1_CFG3
#define CYREG_B0_P0_U0_PLD_IT4
#define CYREG_B0_UDB06_07_MC
#define CYREG_PICU0_INTTYPE5
#define CYREG_B1_UDB06_ST_CTL
#define CYREG_PICU2_INTTYPE3
#define CYREG_B0_UDB11_12_F1
#define CYREG_B1_P2_U1_PLD_IT8
#define CYREG_PRT2_LCD_COM_SEG
#define CYREG_B1_UDB10_MC
#define CYREG_B1_UDB11_12_D1
#define CYREG_PM_AVAIL_SR6
#define CYREG_B0_P0_U1_CFG19
#define CYREG_B0_UDB07_08_D1
#define CYREG_PHUB_CFGMEM3_CFG1
#define CYREG_B1_P5_U1_CFG31
#define CYREG_PHUB_CFGMEM13_CFG1
#define CYREG_B0_P2_U1_CFG26
#define CYREG_B0_P0_U0_CFG1
#define CYREG_RESET_IPOR_CR3
#define CYREG_B0_UDB06_A0_A1
#define CYREG_B1_P5_U1_PLD_ORT3
#define CYREG_TMR3_CNT_CMP1
#define CYREG_B0_UDB03_ST_CTL
#define CYREG_B0_P3_U1_CFG13
#define CYREG_CAN0_RX0_ACRD
#define CYREG_SFR_GPIO15_SEL
#define CYREG_B0_UDB09_F0
#define CYREG_CAN0_RX6_DH
#define CYREG_CLKDIST_DCFG7_CFG0
#define CYREG_B0_P5_U0_CFG16
#define CYREG_CAN0_RX10_AMRD
#define CYREG_PRT2_DBL_SYNC_IN
#define CYREG_B0_UDB09_ST
#define CYREG_B0_P6_U1_CFG31
#define CYREG_ROM_TABLE_CID0
#define CYREG_DWT_FOLD_COUNT
#define CYREG_PWRSYS_WAKE_TR3
#define CYREG_B0_P7_U1_CFG22
#define CYREG_B1_P5_U1_CFG6
#define CYREG_PHUB_CFGMEM22_CFG0
#define CYREG_CAN0_RX12_CMD
#define CYREG_B0_UDB08_09_F1
#define CYREG_B0_P4_U1_DCFG4
#define CYREG_TPIU_FORM_FLUSH_STAT
#define CYREG_PHUB_TDMEM33_ORIG_TD1
#define CYREG_B0_P1_U0_CFG8
#define CYREG_B0_P2_U0_CFG5
#define CYREG_SRAM_CODE32K_MSIZE
#define CYREG_B0_P0_U1_CFG20
#define CYREG_B0_P2_U1_CFG27
#define CYREG_FASTCLK_IMO_CR
#define CYREG_ETM_CFG_CODE
#define CYREG_B0_P2_U1_CFG2
#define CYREG_B0_P3_U0_PLD_ORT1
#define CYREG_CAN0_TX0_ID
#define CYREG_PRT2_PS_ALIAS
#define CYREG_B1_UDB06_ACTL
#define CYREG_CLKDIST_BCFG1
#define CYREG_CAN0_RX9_DL
#define CYREG_B1_UDB05_06_ACTL
#define CYREG_B0_P1_U1_PLD_IT11
#define CYREG_B0_UDB13_D1
#define CYREG_B0_P6_U0_CFG2
#define CYREG_B1_P4_U0_CFG17
#define CYREG_B0_P6_U0_PLD_ORT0
#define CYREG_B0_P3_U1_DCFG1
#define CYREG_B1_P5_U1_CFG27
#define CYREG_B1_P5_U1_CFG7
#define CYREG_FLSHID_CUST_TABLES_DEC_M6
#define CYREG_CLKDIST_WRK1
#define CYREG_PICU5_INTTYPE0
#define CYREG_PHUB_CFGMEM9_CFG1
#define CYREG_B1_P5_U1_PLD_IT0
#define CYREG_FLSHID_CUST_TABLES_LOT_LSB
#define CYREG_B0_P5_U0_CFG29
#define CYREG_CAN0_RX14_CMD
#define CYREG_B1_P2_U1_CFG24
#define CYREG_USB_ARB_INT_EN
#define CYREG_NVIC_PRI_22
#define CYREG_B0_UDB09_D0_D1
#define CYREG_FPB_FP_COMP_4
#define CYREG_B1_UDB04_05_ACTL
#define CYREG_B1_P2_U1_PLD_ORT3
#define CYREG_PICU15_INTTYPE1
#define CYREG_B0_P3_U0_PLD_IT6
#define CYREG_B0_P5_U1_CFG29
#define CYREG_B0_P1_U0_PLD_IT11
#define CYREG_B1_P2_U0_DCFG7
#define CYREG_B0_P1_U0_DCFG7
#define CYREG_B0_P6_U0_CFG8
#define CYREG_B0_P5_U1_MC_CFG_XORFB
#define CYREG_PHUB_TDMEM79_ORIG_TD0
#define CYREG_CLKDIST_ACFG2_CFG1
#define CYREG_CAN0_RX5_AMRD
#define CYREG_B0_UDB11_12_A1
#define CYREG_ETM_ITMISCIN
#define CYREG_B0_P6_U1_CFG15
#define CYREG_B1_P3_U1_PLD_IT1
#define CYREG_B1_UDB10_11_CTL
#define CYREG_PHUB_TDMEM117_ORIG_TD0
#define CYREG_B0_P7_U1_PLD_IT6
#define CYREG_B1_P3_U1_CFG17
#define CYREG_IDMUX_IRQ_CTL2
#define CYREG_B1_P4_U1_CFG15
#define CYREG_PICU1_INTTYPE6
#define CYREG_B1_P2_U1_CFG15
#define CYREG_B0_P6_U1_CFG21
#define CYREG_B0_P3_U0_CFG12
#define CYREG_B0_P4_U0_CFG11
#define CYREG_USB_ARB_EP4_CFG
#define CYREG_NVIC_ACTIVE0
#define CYREG_PHUB_CH2_BASIC_STATUS
#define CYREG_B0_P6_U0_CFG10
#define CYREG_B0_P0_U1_CFG3
#define CYREG_B1_P5_U1_CFG29
#define CYREG_B0_P5_U1_CFG18
#define CYREG_B0_UDB12_13_D0
#define CYREG_B0_UDB07_ST
#define CYREG_B0_P0_U1_CFG4
#define CYREG_PHUB_TDMEM70_ORIG_TD1
#define CYREG_B0_P6_U1_MC_CFG_BYPASS
#define CYREG_B1_UDB09_D1
#define CYREG_B0_UDB14_MSK
#define CYREG_B1_P3_U1_CFG1
#define CYREG_B1_P2_U1_MC_CFG_CEN_CONST
#define CYREG_B0_UDB05_F1
#define CYREG_B0_P0_U1_PLD_IT7
#define CYREG_TPIU_CURRENT_SYNC_PRT_SZ
#define CYREG_B1_P2_U1_PLD_ORT2
#define CYREG_ITM_LOCK_ACCESS
#define CYREG_PHUB_CH19_ACTION
#define CYREG_B0_P5_U0_DCFG7
#define CYREG_B0_UDB04_A0_A1
#define CYREG_B0_P1_U0_CFG18
#define CYREG_PHUB_TDMEM55_ORIG_TD1
#define CYREG_B0_P4_U0_CFG5
#define CYREG_USB_ARB_RW5_RA_MSB
#define CYREG_B0_P5_U0_PLD_IT5
#define CYREG_B1_UDB05_06_MC
#define CYREG_USB_SIE_EP2_CNT1
#define CYREG_B0_P5_U0_DCFG2
#define CYREG_B0_P6_U1_PLD_ORT1
#define CYREG_B0_P0_U1_DCFG4
#define CYREG_B0_P2_U1_CFG8
#define CYREG_PM_AVAIL_SR3
#define CYREG_PRT2_OUT_SEL0
#define CYREG_DFB0_HOLDAM
#define CYREG_B0_P3_U1_PLD_IT4
#define CYREG_B0_P0_U0_PLD_IT9
#define CYREG_B0_P5_U0_CFG0
#define CYREG_B0_P1_U1_PLD_IT9
#define CYREG_B1_UDB07_A0_A1
#define CYREG_NVIC_MEMMAN_FAULT_STATUS
#define CYREG_B0_P7_U0_CFG7
#define CYREG_PHUB_TDMEM51_ORIG_TD1
#define CYREG_B1_UDB09_10_CTL
#define CYREG_B1_P4_U0_PLD_IT2
#define CYREG_B0_P5_U0_PLD_IT3
#define CYREG_B1_P3_U1_CFG27
#define CYREG_PHUB_TDMEM89_ORIG_TD1
#define CYREG_B0_UDB06_F1
#define CYREG_CAN0_RX9_ACR
#define CYREG_B1_UDB09_10_ST
#define CYREG_CLKDIST_DCFG5_CFG0
#define CYREG_B0_P7_U1_CFG23
#define CYREG_B0_P4_U0_CFG24
#define CYREG_PHUB_CFGMEM8_CFG0
#define CYREG_IDMUX_IRQ_CTL7
#define CYREG_B0_P3_U0_PLD_IT8
#define CYREG_PWRSYS_HIB_TR1
#define CYREG_B1_UDB10_MSK_ACTL
#define CYREG_B0_UDB03_CTL
#define CYREG_P3BA_MSTR_HRDATA2
#define CYREG_B1_P2_U1_CFG14
#define CYREG_B1_P3_U0_PLD_IT5
#define CYREG_USB_EP_TYPE
#define CYREG_CAN0_RX0_CMD
#define CYREG_B0_UDB04_05_CTL
#define CYREG_B0_P5_U0_CFG18
#define CYREG_CAN0_TX0_DH
#define CYREG_USB_USBIO_CR0
#define CYREG_B1_P5_U1_CFG3
#define CYREG_B0_P5_U1_CFG14
#define CYREG_B1_P2_U0_CFG6
#define CYREG_CLKDIST_DCFG0_CFG0
#define CYREG_B1_P5_U0_PLD_ORT2
#define CYREG_BCTL0_BCLK_EN0
#define CYREG_CLKDIST_DCFG0_CFG2
#define CYREG_B1_P2_U1_PLD_ORT0
#define CYREG_DEC_OUTSAMPS
#define CYREG_PHUB_TDMEM107_ORIG_TD1
#define CYREG_B0_P2_U0_DCFG6
#define CYREG_PHUB_TDMEM121_ORIG_TD1
#define CYREG_B0_UDB08_ACTL
#define CYREG_B0_UDB09_A1
#define CYREG_B0_P7_U0_CFG16
#define CYREG_B0_P3_U0_MC_CFG_XORFB
#define CYREG_P3BA_XROLL2
#define CYREG_B0_P6_U0_CFG20
#define CYREG_B1_P4_U1_PLD_IT10
#define CYREG_B0_P7_U1_PLD_IT1
#define CYREG_PHUB_TDMEM28_ORIG_TD0
#define CYREG_CLKDIST_DCFG4_CFG0
#define CYREG_FLSHID_CUST_TABLES_DAC2_M7
#define CYREG_PHUB_TDMEM39_ORIG_TD1
#define CYREG_B0_P3_U1_CFG9
#define CYREG_B0_UDB02_03_MSK
#define CYREG_CAN0_RX3_ID
#define CYREG_PHUB_TDMEM47_ORIG_TD1
#define CYREG_B0_P0_U1_PLD_IT2
#define CYREG_B1_P4_U1_DCFG2
#define CYREG_PHUB_TDMEM34_ORIG_TD1
#define CYREG_FLSHID_CUST_TABLES_IMO_24MHZ
#define CYREG_B1_P3_U1_CFG26
#define CYREG_B0_P3_U0_DCFG2
#define CYREG_B0_UDB02_MC
#define CYREG_B0_P2_U1_CFG25
#define CYREG_PHUB_CFGMEM6_CFG1
#define CYREG_B0_P3_U0_CFG27
#define CYREG_B0_P5_U0_CFG7
#define CYREG_B0_P3_U1_DCFG5
#define CYREG_B0_P7_U1_DCFG2
#define CYREG_B1_P2_U1_PLD_IT4
#define CYREG_B1_P5_U1_DCFG2
#define CYREG_B1_P4_U1_PLD_IT2
#define CYREG_B1_P3_U1_CFG7
#define CYREG_NVIC_SYSTICK_CTL
#define CYREG_B1_P4_U0_CFG15
#define CYREG_USB_ARB_EP5_CFG
#define CYREG_B0_P0_U1_CFG22
#define CYREG_B0_P5_U1_CFG0
#define CYREG_B1_P3_U0_CFG28
#define CYREG_B0_UDB10_11_D0
#define CYREG_P3BA_CMP_RSLT1
#define CYREG_CAN0_RX0_ID
#define CYREG_B0_UDB05_F0_F1
#define CYREG_B0_P0_U1_CFG14
#define CYREG_USB_SIE_EP1_CNT1
#define CYREG_B0_UDB05_ST_CTL
#define CYREG_B0_P3_U0_DCFG3
#define CYREG_USB_MEM_DATA_MBASE
#define CYREG_B0_UDB00_01_F0
#define CYREG_B0_UDB09_10_A1
#define CYREG_B0_P4_U1_PLD_ORT0
#define CYREG_NVIC_PRI_26
#define CYREG_PHUB_TDMEM111_ORIG_TD1
#define CYREG_CAN0_RX4_DH
#define CYREG_B0_P3_U0_DCFG0
#define CYREG_PHUB_TDMEM15_ORIG_TD0
#define CYREG_B0_P3_U0_PLD_IT11
#define CYREG_ROM_TABLE_PID2
#define CYREG_B1_UDB10_11_F0
#define CYREG_B0_UDB14_CTL
#define CYREG_B1_UDB07_08_A1
#define CYREG_PHUB_TDMEM124_ORIG_TD0
#define CYREG_B1_P2_U1_CFG7
#define CYREG_PICU4_INTTYPE6
#define CYREG_PHUB_CFGMEM10_CFG1
#define CYREG_B1_UDB06_07_ST
#define CYREG_P3BA_CMP_RSLT4
#define CYREG_B1_P5_U1_DCFG5
#define CYREG_NVIC_CPUID_BASE
#define CYREG_B0_P6_U0_PLD_IT6
#define CYREG_PHUB_CFGMEM17_CFG1
#define CYREG_B0_UDB13_F0_F1
#define CYREG_B1_P3_U1_CFG30
#define CYREG_B0_P0_U1_DCFG6
#define CYREG_B1_P3_U0_CFG21
#define CYREG_USB_ARB_RW2_WA
#define CYREG_B0_UDB12_13_ACTL
#define CYREG_FLSHID_CUST_TABLES_DAC1_M5
#define CYREG_B0_UDB14_F1
#define CYREG_PHUB_TDMEM117_ORIG_TD1
#define CYREG_B1_P3_U0_CFG19
#define CYREG_B0_P3_U0_CFG3
#define CYREG_B0_UDB12_MC
#define CYREG_PRT6_OE_SEL1
#define CYREG_PHUB_TDMEM6_ORIG_TD1
#define CYREG_B0_P4_U0_CFG20
#define CYREG_CAN0_RX5_ACRD
#define CYREG_B0_P2_U1_CFG1
#define CYREG_B1_P3_U1_PLD_ORT0
#define CYREG_USB_SIE_EP5_CNT1
#define CYREG_TPIU_ITATBCTR2
#define CYREG_B0_P6_U1_CFG9
#define CYREG_B0_P3_U0_CFG21
#define CYREG_B0_P0_U0_DCFG0
#define CYREG_B0_P0_U0_DCFG6
#define CYREG_B0_UDB03_ST
#define CYREG_USB_ARB_EP6_SR
#define CYREG_B0_UDB00_F0
#define CYREG_B1_P5_U0_CFG6
#define CYREG_PHUB_CFGMEM15_CFG1
#define CYREG_USB_ARB_RW6_DR
#define CYREG_B1_P3_U0_CFG27
#define CYREG_PHUB_TDMEM108_ORIG_TD0
#define CYREG_USB_SIE_EP2_CNT0
#define CYREG_B1_UDB05_06_A1
#define CYREG_USB_ARB_RW7_WA
#define CYREG_PHUB_CH20_BASIC_CFG
#define CYREG_B1_P5_U1_CFG23
#define CYREG_B1_P5_U1_DCFG4
#define CYREG_B1_P4_U1_MC_CFG_SET_RESET
#define CYREG_B1_UDB08_09_A1
#define CYREG_PHUB_CH16_ACTION
#define CYREG_FLSHID_RSVD_MBASE
#define CYREG_B1_P4_U1_PLD_IT11
#define CYREG_PHUB_CH7_BASIC_CFG
#define CYREG_CORE_DBG_DBG_REG_DATA
#define CYREG_USB_ARB_RW4_RA
#define CYREG_PHUB_TDMEM77_ORIG_TD1
#define CYREG_DFB0_ACU_SRAM_DATA_MBASE
#define CYREG_B0_P0_U0_PLD_IT10
#define CYREG_SLOWCLK_X32_TST
#define CYREG_B0_UDB09_10_F0
#define CYREG_B0_P2_U0_CFG9
#define CYREG_B0_UDB08_D1
#define CYREG_P3BA_X_CURR2
#define CYREG_B0_UDB07_MC
#define CYREG_PHUB_TDMEM101_ORIG_TD1
#define CYREG_PHUB_TDMEM1_ORIG_TD1
#define CYREG_B1_P5_U1_CFG16
#define CYREG_CLKDIST_DCFG7_CFG2
#define CYREG_PHUB_CH17_BASIC_STATUS
#define CYREG_B0_UDB06_F0
#define CYREG_B0_UDB01_02_ACTL
#define CYREG_B1_P2_U0_CFG3
#define CYREG_B0_P5_U1_CFG9
#define CYREG_B1_UDB05_MSK_ACTL
#define CYREG_B1_UDB08_MSK
#define CYREG_B1_UDB10_A0
#define CYREG_USB_ARB_EP2_INT_EN
#define CYREG_B1_UDB04_MC
#define CYREG_PRT5_OUT_SEL0
#define CYREG_PICU15_INTTYPE3
#define CYREG_B0_P2_U0_DCFG3
#define CYREG_CAN0_RX10_DH
#define CYREG_B0_UDB03_04_ACTL
#define CYREG_B0_P2_U1_CFG29
#define CYREG_B0_P7_U0_PLD_IT1
#define CYREG_B1_P2_U1_PLD_IT1
#define CYREG_B1_P2_U1_CFG13
#define CYREG_CAN0_RX11_ACRD
#define CYREG_PHUB_TDMEM99_ORIG_TD0
#define CYREG_B1_P5_U0_CFG27
#define CYREG_PRT4_DR_ALIAS
#define CYREG_B0_P5_U1_PLD_IT2
#define CYREG_PICU12_INTTYPE4
#define CYREG_FASTCLK_XMHZ_CFG0
#define CYREG_B1_P5_U0_CFG13
#define CYREG_B0_UDB10_11_ST
#define CYREG_PHUB_CH17_ACTION
#define CYREG_PHUB_TDMEM126_ORIG_TD0
#define CYREG_B1_UDB10_11_F1
#define CYREG_FLSHID_CUST_TABLES_CMP1_TR0_HS
#define CYREG_B0_P4_U0_CFG6
#define CYREG_FLSHID_CUST_TABLES_CMP0_TR1_HS
#define CYREG_B1_UDB04_05_MSK
#define CYREG_B0_UDB07_08_MSK
#define CYREG_B1_P2_U1_PLD_IT6
#define CYREG_NVIC_INT_CTL_TYPE
#define CYREG_USB_SIE_EP7_CR0
#define CYREG_B0_UDB01_MC
#define CYREG_B0_P7_U0_PLD_IT4
#define CYREG_SRAM_CODE64K_MSIZE
#define CYREG_PHUB_TDMEM22_ORIG_TD0
#define CYREG_B0_P2_U0_MC_CFG_XORFB
#define CYREG_CAN0_RX4_CMD
#define CYREG_PICU15_INTSTAT
#define CYREG_B1_P4_U1_DCFG1
#define CYREG_SPC_DMM_MAP_SRAM_MSIZE
#define CYREG_B0_P0_U0_CFG2
#define CYREG_CAN0_RX2_DL
#define CYREG_B1_UDB11_12_MSK
#define CYREG_B0_P6_U1_CFG12
#define CYREG_B1_P3_U1_DCFG3
#define CYREG_B1_P4_U0_CFG7
#define CYREG_B0_UDB07_A1
#define CYREG_PHUB_TDMEM98_ORIG_TD1
#define CYREG_B0_P5_U0_PLD_IT11
#define CYREG_B0_UDB03_A0
#define CYREG_B0_P3_U0_CFG22
#define CYREG_PHUB_TDMEM66_ORIG_TD1
#define CYREG_B1_P3_U1_CFG25
#define CYREG_TPIU_ITITMDATA
#define CYREG_B1_P2_U0_PLD_IT2
#define CYREG_B1_P3_U0_PLD_IT6
#define CYREG_B0_UDB01_02_A1
#define CYREG_PM_ACT_CFG12
#define CYREG_PHUB_CH12_BASIC_STATUS
#define CYREG_NVIC_PRI_16
#define CYREG_B0_P1_U1_PLD_IT10
#define CYREG_B1_UDB09_10_F1
#define CYREG_DFB0_STAGEB
#define CYREG_B1_P3_U1_PLD_IT8
#define CYREG_B1_P3_U1_CFG14
#define CYREG_B0_UDB14_15_A1
#define CYREG_B0_P1_U0_CFG4
#define CYREG_DFB0_DPA_SRAM_DATA_MBASE
#define CYREG_B1_P5_U0_CFG8
#define CYREG_PM_ACT_CFG7
#define CYREG_PHUB_CH9_BASIC_STATUS
#define CYREG_B0_P4_U1_PLD_IT8
#define CYREG_B0_P3_U0_DCFG1
#define CYREG_B1_UDB04_F1
#define CYREG_B1_P2_U0_CFG5
#define CYREG_PRT2_OE_SEL0
#define CYREG_B0_P3_U1_PLD_IT1
#define CYREG_B0_UDB07_F1
#define CYREG_B0_P5_U0_MC_CFG_CEN_CONST
#define CYREG_DFB0_HOLDAS
#define CYREG_FLSHID_CUST_TABLES_DAC0_M3
#define CYREG_B1_P2_U0_CFG2
#define CYREG_B1_UDB11_ST_CTL
#define CYREG_B0_P3_U1_PLD_IT11
#define CYREG_PHUB_TDMEM20_ORIG_TD1
#define CYREG_B1_P4_U0_CFG0
#define CYREG_PRT1_OE_SEL1
#define CYREG_DFB0_FSM_SRAM_DATA_MBASE
#define CYREG_B0_P3_U1_MC_CFG_BYPASS
#define CYREG_ETM_LOCK_STATUS
#define CYREG_CORE_DBG_DBG_REG_SEL
#define CYREG_FPB_FP_COMP_6
#define CYREG_B0_UDB04_D0_D1
#define CYREG_ETM_FIFOFULL_LEVEL
#define CYREG_B0_P4_U1_CFG6
#define CYREG_IDMUX_IRQ_CTL1
#define CYREG_CAN0_RX11_DL
#define CYREG_B0_UDB15_D1
#define CYREG_DAC0_STROBE
#define CYREG_PRT1_BIT_MASK
#define CYREG_PICU2_INTTYPE6
#define CYREG_B1_UDB07_08_CTL
#define CYREG_PRT0_OE_SEL1
#define CYREG_B0_P4_U0_CFG13
#define CYREG_B1_P3_U0_PLD_IT9
#define CYREG_B0_P6_U0_DCFG5
#define CYREG_PHUB_TDMEM30_ORIG_TD0
#define CYREG_PHUB_TDMEM82_ORIG_TD1
#define CYREG_PWRSYS_BUZZ_TR
#define CYREG_PHUB_TDMEM60_ORIG_TD0
#define CYREG_B0_P1_U0_CFG31
#define CYREG_CAN0_RX7_ACRD
#define CYREG_PM_AVAIL_SR1
#define CYREG_B0_P7_U1_CFG8
#define CYREG_B1_P2_U0_DCFG3
#define CYREG_B1_P5_U0_CFG1
#define CYREG_TPIU_ITCTRL
#define CYREG_CACHERAM_DATA_MSIZE
#define CYREG_B1_UDB08_F0_F1
#define CYREG_B0_P4_U1_CFG7
#define CYREG_B0_UDB11_MC_00
#define CYREG_B0_P0_U1_CFG26
#define CYREG_PHUB_CH14_BASIC_STATUS
#define CYREG_NVIC_INTR_CTRL_STATE
#define CYREG_B0_P5_U0_PLD_ORT0
#define CYREG_B1_P2_U0_CFG25
#define CYREG_PHUB_TDMEM80_ORIG_TD1
#define CYREG_B1_UDB08_ACTL
#define CYREG_B0_P2_U0_DCFG5
#define CYREG_B0_P0_U0_CFG20
#define CYREG_SRAM_DATA16K_MSIZE
#define CYREG_B0_P4_U0_DCFG7
#define CYREG_B1_UDB08_MC_00
#define CYREG_B0_P4_U0_CFG31
#define CYREG_B0_P1_U1_CFG1
#define CYREG_CLKDIST_ACFG0_CFG3
#define CYREG_B1_P3_U0_PLD_IT2
#define CYREG_B0_P0_U0_CFG16
#define CYREG_B0_UDB10_A0
#define CYREG_PRT1_OUT_SEL0
#define CYREG_FLSHID_CUST_TABLES_CMP2_TR1_HS
#define CYREG_CAN0_RX7_CMD
#define CYREG_B0_UDB14_15_F1
#define CYREG_B0_UDB15_CTL
#define CYREG_B1_P2_U0_CFG14
#define CYREG_PICU6_INTTYPE6
#define CYREG_NVIC_PRI_19
#define CYREG_B1_P2_U0_CFG22
#define CYREG_B0_P2_U1_CFG6
#define CYREG_B0_P4_U0_CFG7
#define CYREG_B0_UDB07_A0_A1
#define CYREG_B0_UDB05_CTL
#define CYREG_B0_P5_U0_CFG12
#define CYREG_B0_P2_U1_CFG7
#define CYREG_B0_P5_U0_PLD_IT9
#define CYREG_CAN0_RX14_AMR
#define CYREG_B1_P3_U0_DCFG2
#define CYREG_PRT6_BIT_MASK
#define CYREG_PHUB_CH2_BASIC_CFG
#define CYREG_B0_P0_U0_CFG25
#define CYREG_B1_P2_U0_PLD_IT8
#define CYREG_B1_P3_U0_CFG6
#define CYREG_B1_P3_U0_CFG26
#define CYREG_B0_UDB15_MSK_ACTL
#define CYREG_B0_P0_U0_CFG14
#define CYREG_FLSHID_CUST_TABLES_DAC2_M1
#define CYREG_B1_P2_U1_CFG4
#define CYREG_PHUB_TDMEM116_ORIG_TD1
#define CYREG_B0_P0_U1_PLD_IT0
#define CYREG_B0_UDB06_ACTL
#define CYREG_PHUB_TDMEM10_ORIG_TD0
#define CYREG_FLSHID_CUST_TABLES_WRK_WK
#define CYREG_USB_EP_ACTIVE
#define CYREG_B1_P5_U0_PLD_IT9
#define CYREG_B1_P3_U1_CFG23
#define CYREG_B1_P2_U1_CFG28
#define CYREG_PHUB_CFGMEM7_CFG0
#define CYREG_CAN0_RX10_ACR
#define CYREG_PRT4_LCD_EN
#define CYREG_B0_UDB13_MC
#define CYREG_B0_P4_U0_PLD_ORT3
#define CYREG_B1_UDB11_12_D0
#define CYREG_B1_UDB05_A1
#define CYREG_B1_P5_U1_CFG0
#define CYREG_PHUB_TDMEM6_ORIG_TD0
#define CYREG_B0_P6_U0_MC_CFG_BYPASS
#define CYREG_NVIC_SYSTICK_CAL
#define CYREG_B0_P6_U1_CFG25
#define CYREG_NVIC_PRI_18
#define CYREG_USB_ARB_RW6_RA_MSB
#define CYREG_B0_P0_U0_CFG3
#define CYREG_PHUB_CFGMEM15_CFG0
#define CYREG_B1_P2_U1_DCFG3
#define CYREG_B1_P3_U0_CFG29
#define CYREG_PHUB_TDMEM26_ORIG_TD0
#define CYREG_PM_WAKEUP_CFG1
#define CYREG_B0_UDB01_02_CTL
#define CYREG_B0_P7_U0_PLD_IT3
#define CYREG_B0_UDB11_12_D1
#define CYREG_PRT12_SIO_HYST_EN
#define CYREG_PRT5_BIT_MASK
#define CYREG_B0_P1_U1_CFG21
#define CYREG_B1_P2_U0_MC_CFG_SET_RESET
#define CYREG_B0_P7_U0_DCFG7
#define CYREG_CLKDIST_DCFG3_CFG2
#define CYREG_B0_UDB00_01_A0
#define CYREG_B0_UDB00_F0_F1
#define CYREG_B0_UDB13_14_MC
#define CYREG_B1_P2_U0_CFG13
#define CYREG_B0_UDB15_F0_F1
#define CYREG_PHUB_TDMEM11_ORIG_TD1
#define CYREG_PICU2_INTTYPE2
#define CYREG_B1_P3_U0_MC_CFG_CEN_CONST
#define CYREG_PHUB_CFGMEM4_CFG1
#define CYREG_FASTCLK_PLL_Q
#define CYREG_CAN0_RX6_CMD
#define CYREG_B1_P3_U0_PLD_IT10
#define CYREG_B0_UDB01_02_F0
#define CYREG_B1_P2_U0_CFG26
#define CYREG_B1_P4_U0_CFG19
#define CYREG_B0_P7_U0_PLD_ORT2
#define CYREG_B0_UDB13_14_D0
#define CYREG_PHUB_TDMEM84_ORIG_TD0
#define CYREG_B1_P3_U0_DCFG0
#define CYREG_USB_ARB_RW8_RA
#define CYREG_CAN0_RX10_ID
#define CYREG_B0_UDB10_MSK
#define CYREG_B1_UDB10_11_D1
#define CYREG_CAN0_RX12_ID
#define CYREG_B0_UDB05_ACTL
#define CYREG_B0_P1_U1_DCFG2
#define CYREG_B0_P2_U1_CFG28
#define CYREG_DMA_SRAM_MSIZE
#define CYREG_NVIC_SYSTEM_CONTROL
#define CYREG_B1_P4_U1_DCFG7
#define CYREG_B0_P4_U0_PLD_IT5
#define CYREG_CAN0_TX3_ID
#define CYREG_B1_P2_U0_MC_CFG_BYPASS
#define CYREG_CAN0_RX5_AMR
#define CYREG_B0_UDB13_MSK
#define CYREG_PICU4_INTTYPE2
#define CYREG_B0_UDB07_D1
#define CYREG_PHUB_TDMEM40_ORIG_TD0
#define CYREG_B0_P0_U0_CFG5
#define CYREG_B0_P1_U1_PLD_ORT1
#define CYREG_B0_P7_U1_PLD_ORT3
#define CYREG_PHUB_TDMEM85_ORIG_TD0
#define CYREG_B0_UDB03_04_MSK
#define CYREG_B1_UDB11_A0
#define CYREG_B0_P1_U0_CFG5
#define CYREG_B0_P1_U0_DCFG0
#define CYREG_B0_P4_U1_DCFG5
#define CYREG_IDMUX_DRQ_CTL3
#define CYREG_B0_P6_U1_CFG7
#define CYREG_PRT12_OE_SEL0
#define CYREG_B0_P3_U1_DCFG0
#define CYREG_B0_P2_U1_CFG10
#define CYREG_B1_P3_U0_CFG7
#define CYREG_B0_UDB12_13_ST
#define CYREG_PHUB_TDMEM57_ORIG_TD0
#define CYREG_B0_P0_U1_CFG30
#define CYREG_PHUB_CH22_BASIC_CFG
#define CYREG_CAN0_RX8_ACRD
#define CYREG_PICU1_INTTYPE5
#define CYREG_B1_UDB08_09_D0
#define CYREG_USB_ARB_RW6_WA_MSB
#define CYREG_B1_P3_U1_CFG20
#define CYREG_NVIC_PRI_17
#define CYREG_BCTL0_WAIT_CFG
#define CYREG_CAN0_RX11_ACR
#define CYREG_B0_P4_U1_CFG17
#define CYREG_PICU3_INTTYPE1
#define CYREG_PRT12_DBL_SYNC_IN
#define CYREG_B0_P2_U0_PLD_ORT0
#define CYREG_B0_UDB11_D1
#define CYREG_B1_P3_U0_DCFG3
#define CYREG_B0_P3_U0_CFG13
#define CYREG_USB_EP0_DR6
#define CYREG_P3BA_ABSADDR3
#define CYREG_B0_UDB02_ST_CTL
#define CYREG_CACHERAM_DATA_MBASE
#define CYREG_B0_P6_U0_CFG21
#define CYREG_B0_P3_U0_CFG29
#define CYREG_B0_P2_U0_MC_CFG_CEN_CONST
#define CYREG_B0_UDB12_F1
#define CYREG_B0_P6_U0_PLD_IT8
#define CYREG_B0_UDB09_CTL
#define CYREG_MLOGIC_SEG_CR
#define CYREG_B1_UDB09_ST_CTL
#define CYREG_PHUB_CH23_BASIC_STATUS
#define CYREG_USB_ARB_EP7_SR
#define CYREG_B0_P6_U0_CFG0
#define CYREG_B0_UDB02_D1
#define CYREG_B1_P4_U1_CFG0
#define CYREG_B0_UDB03_04_ST
#define CYREG_B0_P3_U1_PLD_ORT2
#define CYREG_B1_UDB08_ST
#define CYREG_B0_P2_U0_MC_CFG_SET_RESET
#define CYREG_CAN0_RX8_ACR
#define CYREG_B1_UDB07_08_F1
#define CYREG_B1_P4_U1_PLD_IT7
#define CYREG_B0_P7_U1_MC_CFG_CEN_CONST
#define CYREG_B0_UDB10_MC_00
#define CYREG_B0_P1_U0_DCFG1
#define CYREG_B1_P4_U0_DCFG6
#define CYREG_P3BA_MSTR_HRDATA3
#define CYREG_B0_UDB02_ACTL
#define CYREG_B1_P3_U0_CFG14
#define CYREG_B1_P2_U0_PLD_IT0
#define CYREG_B0_P5_U1_CFG17
#define CYREG_B1_P4_U0_MC_CFG_BYPASS
#define CYREG_B0_P0_U0_CFG15
#define CYREG_B0_P2_U1_PLD_ORT3
#define CYREG_B1_P2_U0_CFG15
#define CYREG_B0_UDB14_15_ST
#define CYREG_B0_P7_U0_PLD_IT9
#define CYREG_B0_UDB07_F0
#define CYREG_CAN0_RX1_DL
#define CYREG_B1_P3_U0_CFG17
#define CYREG_B0_P3_U1_CFG6
#define CYREG_B0_P1_U0_CFG12
#define CYREG_PHUB_TDMEM115_ORIG_TD1
#define CYREG_BCTL1_BANK_CTL
#define CYREG_P3BA_X_START1
#define CYREG_B0_P7_U1_CFG9
#define CYREG_CAN0_RX1_ACRD
#define CYREG_I2C_CLK_DIV1
#define CYREG_CLKDIST_ACFG0_CFG0
#define CYREG_DFB0_STAGEAM
#define CYREG_CORE_DBG_DBG_HLT_CS
#define CYREG_ETM_DEV_TYPE
#define CYREG_CLKDIST_DCFG1_CFG2
#define CYREG_PRT3_PS_ALIAS
#define CYREG_CAN0_RX13_ACR
#define CYREG_CAN0_RX14_AMRD
#define CYREG_FLSHID_CUST_TABLES_DAC0_M5
#define CYREG_CAN0_RX15_DH
#define CYREG_FLSHID_CUST_TABLES_DAC0_M6
#define CYREG_MLOGIC_CPU_SCR_CPU_SCR
#define CYREG_CLKDIST_DCFG6_CFG0
#define CYREG_B1_P3_U1_MC_CFG_BYPASS
#define CYREG_NVIC_VECT_OFFSET
#define CYREG_PHUB_TDMEM97_ORIG_TD0
#define CYREG_B0_P0_U0_CFG19
#define CYREG_PHUB_CFGMEM0_CFG0
#define CYREG_B0_P2_U0_PLD_ORT1
#define CYREG_PHUB_TDMEM101_ORIG_TD0
#define CYREG_B0_UDB14_D0
#define CYREG_B0_P7_U1_PLD_IT7
#define CYREG_B0_P5_U0_PLD_ORT1
#define CYREG_ROM_TABLE_NVIC
#define CYREG_NVIC_SETPEND0
#define CYREG_PHUB_TDMEM8_ORIG_TD1
#define CYREG_TPIU_DEVTYPE
#define CYREG_NVIC_CFG_CONTROL
#define CYREG_B0_P7_U0_PLD_ORT0
#define CYREG_B0_P0_U1_CFG9
#define CYREG_B0_P1_U1_PLD_IT2
#define CYREG_PHUB_TDMEM61_ORIG_TD1
#define CYREG_PHUB_TDMEM18_ORIG_TD0
#define CYREG_NVIC_BUS_FAULT_ADD
#define CYREG_B1_UDB10_11_ACTL
#define CYREG_B0_P5_U1_CFG7
#define CYREG_FASTCLK_PLL_CFG1
#define CYREG_SPC_CPU_DATA
#define CYREG_B0_P0_U0_MC_CFG_BYPASS
#define CYREG_B0_P5_U0_DCFG3
#define CYREG_PHUB_TDMEM59_ORIG_TD0
#define CYREG_B0_UDB13_14_F0
#define CYREG_CAN0_TX3_DH
#define CYREG_PM_AVAIL_SR5
#define CYREG_PHUB_TDMEM95_ORIG_TD1
#define CYREG_B0_P1_U1_CFG31
#define CYREG_B0_UDB06_ST_CTL
#define CYREG_DFB0_FSM_SRAM_DATA_MSIZE
#define CYREG_B1_P4_U0_CFG27
#define CYREG_FLSHID_MFG_CFG_CMP0_TR1
#define CYREG_B1_P3_U0_CFG15
#define CYREG_B1_UDB08_09_F1
#define CYREG_I2C_TMOUT_CFG1
#define CYREG_B0_P3_U1_CFG25
#define CYREG_B0_P4_U1_DCFG6
#define CYREG_B0_P4_U0_DCFG2
#define CYREG_B1_UDB05_06_D1
#define CYREG_FLSHID_CUST_TABLES_DAC1_M6
#define CYREG_B0_P7_U1_CFG0
#define CYREG_B0_P2_U1_CFG11
#define CYREG_PHUB_TDMEM61_ORIG_TD0
#define CYREG_B0_P4_U1_PLD_IT11
#define CYREG_PICU0_DISABLE_COR
#define CYREG_PHUB_TDMEM73_ORIG_TD1
#define CYREG_PICU12_INTTYPE5
#define CYREG_EE_DATA_MSIZE
#define CYREG_BCTL0_BCLK_EN2
#define CYREG_CAN0_RX14_ID
#define CYREG_B0_P2_U0_CFG19
#define CYREG_B0_P4_U1_CFG22
#define CYREG_B0_UDB07_MC_00
#define CYREG_B0_P7_U0_CFG20
#define CYREG_PHUB_TDMEM97_ORIG_TD1
#define CYREG_B0_P4_U0_CFG28
#define CYREG_B1_P5_U0_MC_CFG_BYPASS
#define CYREG_B1_UDB11_12_ST
#define CYREG_B0_P2_U0_PLD_IT1
#define CYREG_PHUB_TDMEM75_ORIG_TD0
#define CYREG_B1_P2_U0_DCFG4
#define CYREG_B1_P5_U1_CFG22
#define CYREG_B0_P3_U0_CFG1
#define CYREG_B0_P1_U1_CFG11
#define CYREG_CAN0_RX10_DL
#define CYREG_B0_UDB11_F0_F1
#define CYREG_B1_P5_U1_CFG21
#define CYREG_PHUB_TDMEM64_ORIG_TD1
#define CYREG_OPAMP0_RSVD
#define CYREG_NVIC_SYS_PRIO_HANDLER_12_15
#define CYREG_B0_P7_U0_DCFG6
#define CYREG_PRT12_INP_DIS
#define CYREG_B0_UDB11_12_A0
#define CYREG_B0_UDB04_CTL
#define CYREG_B1_P2_U1_DCFG6
#define CYREG_B0_P3_U1_MC_CFG_SET_RESET
#define CYREG_B1_P4_U1_CFG10
#define CYREG_ETM_CLM_TAG_CLR
#define CYREG_B1_UDB11_ST
#define CYREG_FPB_FP_COMP_1
#define CYREG_B0_UDB05_D1
#define CYREG_PHUB_TDMEM26_ORIG_TD1
#define CYREG_B0_P0_U0_CFG13
#define CYREG_SRAM_DATA64K_MBASE
#define CYREG_USB_ARB_EP4_SR
#define CYREG_FLASH_DATA_MSIZE
#define CYREG_B1_UDB11_MC
#define CYREG_B0_UDB00_MSK
#define CYREG_B0_UDB05_A0_A1
#define CYREG_NVIC_BUS_FAULT_STATUS
#define CYREG_B0_UDB10_F0_F1
#define CYREG_B0_UDB10_11_F0
#define CYREG_PHUB_CH11_BASIC_CFG
#define CYREG_CAN0_RX3_ACR
#define CYREG_B0_UDB03_04_A1
#define CYREG_B0_UDB11_12_MSK
#define CYREG_PICU12_INTTYPE2
#define CYREG_CAN0_RX3_ACRD
#define CYREG_PHUB_TDMEM16_ORIG_TD1
#define CYREG_CAN0_RX6_AMR
#define CYREG_B0_P7_U1_DCFG3
#define CYREG_B0_P2_U0_CFG18
#define CYREG_SRAM_CODE16K_MBASE
#define CYREG_B0_P0_U1_PLD_IT11
#define CYREG_FLSHID_CUST_TABLES_DAC1_M3
#define CYREG_B1_P3_U0_CFG18
#define CYREG_B0_P2_U0_MC_CFG_BYPASS
#define CYREG_IDMUX_IRQ_CTL3
#define CYREG_DFB0_HOLDBH
#define CYREG_B1_UDB09_10_ACTL
#define CYREG_FLSHID_CUST_TABLES_DAC3_M8
#define CYREG_B1_P2_U1_CFG17
#define CYREG_B0_P0_U1_PLD_IT5
#define CYREG_PHUB_CH2_ACTION
#define CYREG_B0_P4_U1_PLD_IT1
#define CYREG_PHUB_TDMEM126_ORIG_TD1
#define CYREG_PRT2_BIT_MASK
#define CYREG_B0_UDB02_D0_D1
#define CYREG_B0_P2_U0_DCFG4
#define CYREG_PICU6_INTSTAT
#define CYREG_B0_UDB02_03_A1
#define CYREG_B1_P5_U0_PLD_ORT1
#define CYREG_B0_P6_U1_CFG17
#define CYREG_PM_MODE_CFG0
#define CYREG_P3BA_CMP_RSLT2
#define CYREG_PHUB_CH21_BASIC_STATUS
#define CYREG_B1_P2_U1_DCFG7
#define CYREG_FLSHID_CUST_TABLES_IMO_12MHZ
#define CYREG_CAN0_RX14_DL
#define CYREG_B0_P7_U1_DCFG6
#define CYREG_B1_P4_U1_CFG12
#define CYREG_B0_P7_U0_CFG21
#define CYREG_FPB_FP_COMP_3
#define CYREG_PWRSYS_BREF_TR
#define CYREG_USB_ARB_RW8_RA_MSB
#define CYREG_PHUB_CFGMEM1_CFG1
#define CYREG_CAN0_RX5_CMD
#define CYREG_CAN0_RX7_ACR
#define CYREG_USB_ARB_RW1_WA
#define CYREG_B1_P4_U1_CFG26
#define CYREG_B0_UDB03_D0_D1
#define CYREG_B0_P0_U1_CFG2
#define CYREG_B0_P7_U1_CFG25
#define CYREG_B0_UDB08_09_ST
#define CYREG_B0_UDB08_MC_00
#define CYREG_B0_P3_U0_CFG16
#define CYREG_B0_UDB03_ACTL
#define CYREG_B0_P7_U1_CFG6
#define CYREG_B1_P2_U1_DCFG2
#define CYREG_B0_UDB04_05_D1
#define CYREG_B0_P7_U0_CFG4
#define CYREG_B1_P4_U1_PLD_IT1
#define CYREG_PM_ACT_CFG13
#define CYREG_PM_AVAIL_CR5
#define CYREG_USB_ARB_RW4_DR
#define CYREG_B0_P5_U1_PLD_IT0
#define CYREG_B0_P3_U0_PLD_IT7
#define CYREG_B0_P3_U1_CFG10
#define CYREG_FLSHID_CUST_MDATA_MSIZE
#define CYREG_B0_UDB01_ACTL
#define CYREG_B0_P3_U0_PLD_IT2
#define CYREG_CAN0_TX5_ID
#define CYREG_PICU6_INTTYPE1
#define CYREG_PICU5_INTTYPE2
#define CYREG_ETM_OS_LOCK_STATUS
#define CYREG_P3BA_DATCFG2
#define CYREG_B0_P2_U0_PLD_IT6
#define CYREG_B1_P4_U0_CFG2
#define CYREG_PRT4_DBL_SYNC_IN
#define CYREG_CAN0_RX2_DH
#define CYREG_DFB0_DPA_SRAM_DATA_MSIZE
#define CYREG_B0_P0_U0_PLD_IT7
#define CYREG_CAN0_RX2_AMR
#define CYREG_B1_P2_U0_PLD_IT6
#define CYREG_ETM_TRACE_EN_CTRL1
#define CYREG_B0_P5_U1_DCFG1
#define CYREG_B0_P1_U0_CFG13
#define CYREG_B1_P2_U1_MC_CFG_BYPASS
#define CYREG_PRT6_SYNC_OUT
#define CYREG_B1_P4_U0_DCFG1
#define CYREG_B1_P4_U1_CFG18
#define CYREG_PANTHER_STCALIB_CFG
#define CYREG_B0_P7_U1_PLD_ORT2
#define CYREG_CAN0_RX14_ACR
#define CYREG_CAN0_RX6_ACR
#define CYREG_CAN0_TX0_CMD
#define CYREG_NVIC_SYSTICK_RELOAD
#define CYREG_PRT1_OUT_SEL1
#define CYREG_B0_UDB06_07_F1
#define CYREG_B0_P4_U1_CFG0
#define CYREG_B0_UDB10_11_MSK
#define CYREG_B0_P3_U1_CFG29
#define CYREG_PHUB_TDMEM104_ORIG_TD0
#define CYREG_B0_UDB05_ST
#define CYREG_PICU2_INTSTAT
#define CYREG_B0_P1_U0_DCFG6
#define CYREG_B0_UDB10_MC
#define CYREG_B1_P5_U0_CFG11
#define CYREG_B0_P7_U0_MC_CFG_BYPASS
#define CYREG_B1_UDB06_MC_00
#define CYREG_B0_P5_U1_CFG3
#define CYREG_B0_P3_U1_CFG16
#define CYREG_B0_P0_U0_MC_CFG_XORFB
#define CYREG_B0_UDB15_MSK
#define CYREG_B1_P4_U1_DCFG5
#define CYREG_B1_P4_U1_PLD_ORT1
#define CYREG_ETM_TRIG_EVENT
#define CYREG_ETM_OS_LOCK_ACCESS
#define CYREG_NVIC_HARD_FAULT_STATUS
#define CYREG_B0_UDB02_03_MC
#define CYREG_PHUB_CFGMEM14_CFG0
#define CYREG_PHUB_CFGMEM19_CFG0
#define CYREG_PHUB_TDMEM73_ORIG_TD0
#define CYREG_B0_UDB05_MC
#define CYREG_B1_UDB11_12_A0
#define CYREG_TMR1_CNT_CMP0
#define CYREG_USB_SIE_EP4_CNT1
#define CYREG_B0_UDB01_D0
#define CYREG_PHUB_TDMEM19_ORIG_TD0
#define CYREG_USB_SIE_EP5_CNT0
#define CYREG_B1_P5_U1_CFG25
#define CYREG_IDMUX_IRQ_CTL6
#define CYREG_B0_P0_U1_PLD_IT4
#define CYREG_B0_P1_U1_CFG18
#define CYREG_PHUB_TDMEM36_ORIG_TD1
#define CYREG_B0_P2_U1_PLD_IT7
#define CYREG_PM_STBY_CFG0
#define CYREG_B1_P3_U1_CFG21
#define CYREG_B0_UDB04_05_A1
#define CYREG_B0_P2_U0_CFG15
#define CYREG_B1_UDB04_F0_F1
#define CYREG_B0_UDB10_F1
#define CYREG_B1_UDB05_A0
#define CYREG_B0_P2_U1_CFG5
#define CYREG_B0_P1_U0_CFG1
#define CYREG_B1_P4_U0_CFG6
#define CYREG_FLSHID_CUST_TABLES_DAC1_M1
#define CYREG_B1_P5_U0_CFG9
#define CYREG_ETM_LOCK_ACCESS
#define CYREG_B0_P7_U0_MC_CFG_SET_RESET
#define CYREG_B1_P5_U0_PLD_IT3
#define CYREG_NVIC_PRI_13
#define CYREG_USB_SIE_EP3_CNT1
#define CYREG_PHUB_TDMEM113_ORIG_TD1
#define CYREG_B0_P2_U1_PLD_IT11
#define CYREG_PHUB_TDMEM125_ORIG_TD1
#define CYREG_B1_UDB05_ACTL
#define CYREG_BCTL0_BCLK_EN1
#define CYREG_B0_UDB10_F0
#define CYREG_B0_P5_U0_CFG13
#define CYREG_B0_P3_U0_CFG8
#define CYREG_CLKDIST_DCFG6_CFG1
#define CYREG_B0_P6_U0_CFG23
#define CYREG_B0_UDB02_MC_00
#define CYREG_B1_P5_U1_CFG5
#define CYREG_B0_P7_U1_PLD_IT3
#define CYREG_B0_UDB12_MSK
#define CYREG_PICU5_INTTYPE6
#define CYREG_B0_UDB04_MSK_ACTL
#define CYREG_SRAM_CODE64K_MBASE
#define CYREG_PHUB_TDMEM74_ORIG_TD1
#define CYREG_B1_P5_U0_CFG18
#define CYREG_B0_P2_U1_CFG21
#define CYREG_B0_UDB06_07_ST
#define CYREG_PHUB_TDMEM79_ORIG_TD1
#define CYREG_B0_P7_U0_DCFG4
#define CYREG_PHUB_TDMEM43_ORIG_TD0
#define CYREG_B0_P1_U0_PLD_IT4
#define CYREG_PHUB_TDMEM41_ORIG_TD0
#define CYREG_B0_P1_U0_MC_CFG_SET_RESET
#define CYREG_B0_P2_U0_PLD_IT5
#define CYREG_B0_P7_U1_DCFG1
#define CYREG_B0_UDB10_D0
#define CYREG_B0_P1_U1_CFG30
#define CYREG_B1_UDB05_ST
#define CYREG_B0_UDB03_04_D0
#define CYREG_PRT4_CAPS_SEL
#define CYREG_PHUB_TDMEM19_ORIG_TD1
#define CYREG_B1_P4_U1_CFG23
#define CYREG_B1_UDB05_ST_CTL
#define CYREG_B0_P5_U1_CFG10
#define CYREG_B0_P2_U0_CFG7
#define CYREG_B0_P6_U1_DCFG2
#define CYREG_B0_P6_U0_CFG3
#define CYREG_B0_UDB06_07_F0
#define CYREG_USB_SIE_EP8_CNT0
#define CYREG_PHUB_TDMEM68_ORIG_TD1
#define CYREG_B0_UDB04_MC_00
#define CYREG_P3BA_MSTR_HRDATA4
#define CYREG_B0_P3_U1_PLD_IT7
#define CYREG_CAN0_RX10_ACRD
#define CYREG_PICU3_INTTYPE4
#define CYREG_CAN0_RX0_ACR
#define CYREG_FLSHID_CUST_TABLES_DAC2_M4
#define CYREG_B0_P4_U0_MC_CFG_XORFB
#define CYREG_B0_UDB12_MC_00
#define CYREG_FLSHID_CUST_TABLES_DAC1_M7
#define CYREG_B1_P5_U1_CFG26
#define CYREG_USB_EP0_DR0
#define CYREG_B0_P3_U0_CFG7
#define CYREG_CAN0_RX13_CMD
#define CYREG_B0_UDB13_14_D1
#define CYREG_B1_P3_U1_CFG0
#define CYREG_B0_UDB04_05_ST
#define CYREG_B1_P3_U1_CFG6
#define CYREG_USB_ARB_EP5_SR
#define CYREG_P3BA_ABSADDR2
#define CYREG_PHUB_TDMEM40_ORIG_TD1
#define CYREG_B1_P3_U1_MC_CFG_CEN_CONST
#define CYREG_DWT_PC_SAMPLE
#define CYREG_USB_ARB_RW3_WA_MSB
#define CYREG_B0_P4_U1_PLD_IT9
#define CYREG_PM_MODE_CFG1
#define CYREG_B0_UDB02_03_CTL
#define CYREG_B0_UDB14_15_MSK
#define CYREG_B0_UDB12_A1
#define CYREG_B0_UDB05_06_MSK
#define CYREG_B0_P3_U0_DCFG6
#define CYREG_PHUB_TDMEM56_ORIG_TD0
#define CYREG_CAN0_RX6_ACRD
#define CYREG_B1_P4_U0_DCFG3
#define CYREG_B0_P1_U1_PLD_ORT0
#define CYREG_B0_UDB00_A0
#define CYREG_B0_UDB02_MSK
#define CYREG_B0_UDB00_01_A1
#define CYREG_B0_P1_U0_PLD_IT6
#define CYREG_MLOGIC_SEG_CFG0
#define CYREG_B1_P2_U0_CFG1
#define CYREG_B0_P6_U0_DCFG2
#define CYREG_EXTMEM_DATA_MBASE
#define CYREG_B1_P4_U1_CFG30
#define CYREG_B0_UDB02_03_ST
#define CYREG_B0_P1_U0_DCFG2
#define CYREG_B1_UDB09_CTL
#define CYREG_B1_P3_U0_PLD_ORT2
#define CYREG_B1_P5_U1_CFG4
#define CYREG_B0_UDB04_F0
#define CYREG_PHUB_TDMEM77_ORIG_TD0
#define CYREG_B0_UDB06_F0_F1
#define CYREG_B0_P5_U1_CFG28
#define CYREG_B1_P3_U0_PLD_IT0
#define CYREG_B0_P4_U0_CFG22
#define CYREG_B1_UDB10_11_A1
#define CYREG_CLKDIST_DCFG3_CFG1
#define CYREG_B1_UDB06_CTL
#define CYREG_PHUB_TDMEM91_ORIG_TD0
#define CYREG_B0_P1_U0_CFG10
#define CYREG_B1_P5_U1_PLD_IT4
#define CYREG_IDMUX_IRQ_CTL4
#define CYREG_B0_UDB15_MC
#define CYREG_TPIU_PROTOCOL
#define CYREG_B1_P3_U1_CFG15
#define CYREG_PRT5_OE_SEL0
#define CYREG_B0_UDB14_15_MC
#define CYREG_B0_P7_U0_CFG9
#define CYREG_PRT6_OE_SEL0
#define CYREG_CAN0_TX7_DH
#define CYREG_B0_UDB03_A1
#define CYREG_B0_P7_U1_CFG21
#define CYREG_B0_UDB03_MSK
#define CYREG_B0_P7_U1_CFG14
#define CYREG_B1_P4_U0_PLD_IT4
#define CYREG_PM_ACT_CFG1
#define CYREG_PRT6_INP_DIS
#define CYREG_B1_P4_U1_CFG20
#define CYREG_B1_P2_U0_CFG18
#define CYREG_DWT_CYCLE_COUNT
#define CYREG_B1_P4_U0_CFG1
#define CYREG_CLKDIST_ACFG1_CFG0
#define CYREG_B0_UDB10_11_F1
#define CYREG_B0_P6_U1_PLD_IT9
#define CYREG_B0_P7_U1_PLD_IT2
#define CYREG_B0_P3_U1_PLD_IT3
#define CYREG_B0_P0_U1_PLD_IT3
#define CYREG_PM_STBY_CFG13
#define CYREG_B1_UDB05_D1
#define CYREG_B0_P6_U0_CFG9
#define CYREG_PHUB_TDMEM33_ORIG_TD0
#define CYREG_PHUB_TDMEM0_ORIG_TD1
#define CYREG_B0_UDB08_09_CTL
#define CYREG_CLKDIST_ACFG3_CFG1
#define CYREG_B1_P4_U1_CFG6
#define CYREG_B1_P3_U1_PLD_IT5
#define CYREG_CAN0_TX5_CMD
#define CYREG_B0_UDB06_ST
#define CYREG_B0_P3_U0_MC_CFG_CEN_CONST
#define CYREG_B0_UDB08_ST_CTL
#define CYREG_B1_P5_U1_CFG14
#define CYREG_B0_P2_U0_PLD_IT3
#define CYREG_B1_P3_U0_DCFG7
#define CYREG_B0_P2_U0_PLD_ORT2
#define CYREG_B0_P1_U1_PLD_IT0
#define CYREG_PICU1_INTSTAT
#define CYREG_B1_P3_U1_CFG4
#define CYREG_B0_P1_U0_CFG20
#define CYREG_B1_P4_U1_CFG14
#define CYREG_B0_UDB10_11_MC
#define CYREG_USB_ARB_RW1_DR
#define CYREG_B0_P3_U0_DCFG4
#define CYREG_PHUB_CH7_ACTION
#define CYREG_B1_P2_U1_PLD_IT9
#define CYREG_SFR_GPIRD15
#define CYREG_B0_P7_U1_CFG12
#define CYREG_CAN0_RX6_ID
#define CYREG_B0_P0_U0_CFG18
#define CYREG_PRT4_BIT_MASK
#define CYREG_B0_UDB12_13_MSK
#define CYREG_B0_P1_U1_CFG29
#define CYREG_B1_UDB05_A0_A1
#define CYREG_PRT5_SYNC_OUT
#define CYREG_DFB0_STAGEBH
#define CYREG_PRT1_OE_SEL0
#define CYREG_B0_UDB04_ACTL
#define CYREG_ETM_ITATBCTR0
#define CYREG_B1_P4_U1_DCFG6
#define CYREG_PHUB_TDMEM24_ORIG_TD1
#define CYREG_B1_P4_U1_CFG7
#define CYREG_B0_P7_U0_CFG27
#define CYREG_B0_P3_U1_CFG2
#define CYREG_B1_UDB07_08_A0
#define CYREG_B0_UDB14_A1
#define CYREG_PICU5_INTTYPE3
#define CYREG_PHUB_TDMEM52_ORIG_TD1
#define CYREG_B0_UDB07_08_ST
#define CYREG_B0_P6_U0_DCFG1
#define CYREG_B0_P5_U1_CFG6
#define CYREG_PHUB_TDMEM50_ORIG_TD1
#define CYREG_B1_P2_U1_CFG9
#define CYREG_CLKDIST_DCFG6_CFG2
#define CYREG_B1_P2_U0_CFG11
#define CYREG_B1_P4_U1_PLD_IT3
#define CYREG_FLSHID_MFG_CFG_CMP3_TR0
#define CYREG_B0_UDB13_ST_CTL
#define CYREG_B1_UDB08_A0
#define CYREG_PICU0_INTTYPE3
#define CYREG_B0_UDB10_D0_D1
#define CYREG_B0_P1_U0_CFG11
#define CYREG_B0_P6_U0_CFG28
#define CYREG_B1_UDB06_A1
#define CYREG_B1_UDB04_D0_D1
#define CYREG_B0_P7_U0_CFG11
#define CYREG_CAN0_TX7_ID
#define CYREG_B1_P4_U0_DCFG7
#define CYREG_B0_P6_U0_CFG24
#define CYREG_B1_P2_U1_CFG8
#define CYREG_B1_P3_U0_CFG10
#define CYREG_CLKDIST_DCFG4_CFG2
#define CYREG_B1_UDB07_ST
#define CYREG_B0_P1_U1_DCFG0
#define CYREG_TMR0_CNT_CMP1
#define CYREG_B0_P1_U1_PLD_IT3
#define CYREG_NVIC_PRI_24
#define CYREG_B1_UDB10_A0_A1
#define CYREG_B0_P4_U0_PLD_ORT0
#define CYREG_B0_P2_U1_MC_CFG_CEN_CONST
#define CYREG_B1_UDB05_D0_D1
#define CYREG_FLSHID_CUST_MDATA_MBASE
#define CYREG_PHUB_CH18_BASIC_CFG
#define CYREG_B0_UDB09_MSK_ACTL
#define CYREG_SFR_GPIRD12
#define CYREG_B0_P4_U1_CFG16
#define CYREG_CAN0_RX5_DL
#define CYREG_B0_P0_U0_CFG21
#define CYREG_B0_P0_U0_PLD_IT2
#define CYREG_PICU3_INTSTAT
#define CYREG_B1_P5_U0_PLD_IT11
#define CYREG_B0_UDB05_06_F0
#define CYREG_USB_ARB_RW8_WA
#define CYREG_PHUB_TDMEM115_ORIG_TD0
#define CYREG_B1_UDB11_12_MC
#define CYREG_B0_P6_U0_CFG13
#define CYREG_B0_UDB04_05_MSK
#define CYREG_B1_P4_U0_PLD_IT7
#define CYREG_B1_P5_U1_PLD_IT2
#define CYREG_B0_P6_U1_DCFG1
#define CYREG_B0_P0_U0_MC_CFG_SET_RESET
#define CYREG_PHUB_TDMEM85_ORIG_TD1
#define CYREG_B0_P0_U1_CFG16
#define CYREG_B0_P3_U1_CFG20
#define CYREG_DWT_FUNCTION_0
#define CYREG_B1_UDB08_09_MSK
#define CYREG_PHUB_CFGMEM6_CFG0
#define CYREG_USB_SIE_EP1_CNT0
#define CYREG_B0_P5_U0_PLD_ORT3
#define CYREG_PRT2_INP_DIS
#define CYREG_B1_P3_U0_PLD_IT11
#define CYREG_I2C_TMOUT_CFG0
#define CYREG_B0_P5_U1_DCFG4
#define CYREG_B1_P5_U1_PLD_IT6
#define CYREG_B0_P7_U1_PLD_IT0
#define CYREG_PM_STBY_CFG10
#define CYREG_EMIF_MEMCLK_DIV
#define CYREG_CAN0_RX12_AMRD
#define CYREG_B1_UDB07_08_MC
#define CYREG_B0_UDB02_F1
#define CYREG_B0_P7_U1_PLD_ORT1
#define CYREG_B1_UDB09_MSK
#define CYREG_B1_UDB08_CTL
#define CYREG_B0_P7_U0_CFG25
#define CYREG_B0_UDB11_A0
#define CYREG_B1_UDB05_F0_F1
#define CYREG_PHUB_CFGMEM23_CFG1
#define CYREG_B1_P3_U0_PLD_ORT1
#define CYREG_B1_P4_U0_CFG10
#define CYREG_B1_P4_U1_CFG11
#define CYREG_PM_AVAIL_CR6
#define CYREG_BCTL0_UDB_TEST_3
#define CYREG_SRAM_CODE16K_MSIZE
#define CYREG_FLSHID_CUST_TABLES_DEC_M2
#define CYREG_FLSHID_CUST_TABLES_DEC_M4
#define CYREG_B0_P1_U1_CFG27
#define CYREG_B0_UDB02_A0_A1
#define CYREG_DEC_OUTSAMPH
#define CYREG_PICU3_INTTYPE6
#define CYREG_B0_P7_U0_MC_CFG_CEN_CONST
#define CYREG_B0_P5_U1_PLD_IT10
#define CYREG_USB_ARB_RW3_RA_MSB
#define CYREG_BCTL1_UDB_TEST_3
#define CYREG_B0_UDB00_01_D1
#define CYREG_B0_P5_U1_CFG5
#define CYREG_B1_P3_U0_CFG22
#define CYREG_PHUB_CH14_BASIC_CFG
#define CYREG_B1_P5_U1_CFG10
#define CYREG_B0_P1_U0_CFG17
#define CYREG_PICU5_DISABLE_COR
#define CYREG_B0_UDB07_08_A1
